Zero-power OR gate

Details Zero-power OR gate Zero-power OR gate

1993-09-08

1995-10-10

Hudspeth, David R.

Electronic digital logic circuitry

Accelerating switching

326 37, 326 98, 327544, H03R 1709

Patent

active

054574048

ABSTRACT:
A zero-power wide OR gate for implementing the "sum" of the "sum of product terms" in a programmable logic device (PLD). The wide OR gate includes a single additional input transistor for each added "product term" input from a sense amplifier. The wide OR gate further includes circuitry to decouple the current supply from sense amplifiers turned on during sleep mode to limit power utilized. To increase operation speed, the wide OR gate utilizes a strong current source when sense amplifiers are all turned off to quickly pull up internal circuitry while utilizing a weak current source when sense amplifiers turn on to allow the sense amplifiers to more easily overcome the current supply. To further increase speed, the wide OR gate includes a threshold shifting transistor to shift the pull down threshold of the output inverter for when all sense amplifiers are turned off while shifting the threshold back for when a sense amplifier transitions to on.

REFERENCES:
patent: 4503341 (1985-03-01), Shah
patent: 4563598 (1986-01-01), Oritani
patent: 4620116 (1986-10-01), Ozawa
patent: 4831285 (1989-05-01), Gaiser
patent: 4959564 (1990-09-01), Steele

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