Zero power memory cell with reduced threshold voltage

Details Zero power memory cell with reduced threshold voltage Zero power memory cell with reduced threshold voltage

2003-07-24

2004-05-18

Hoang, Huan (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S336000, C257S344000, C257S345000, C257S404000

Reexamination Certificate

active

06737702

ABSTRACT:

TECHNICAL FIELD
The present invention is directed to improvements in memory cells using no power, and in particular, to improvements in data retention in such cells by lowering the threshold voltage of one or more transistors used in the cell.
BACKGROUND
Nonvolatile memory cells are used in a variety of applications. As with many semiconductor device technologies, non-volatile memory device designers strive to increase the performance of devices, while decreasing device dimensions and consequently increasing circuit density. Designers also strive to reduce power requirements of devices by reducing program and erase voltage requirements.
Generally, arrays of individual memory cells are formed on a single substrate and combined with sense and read circuitry, and connected by row-wise and column-wise conductive regions or metallic conductors to allow for array wide bulk program and erase as well as selected bit programming.
Ideally, cells are designed to be reliable in retaining the state of their programming (either having charged or discharged floating gates) with no power attached to the cell.
Over time, the EEPROM memory cell will be written and erased repeatedly as data is stored and removed from the memory cell. Since the EEPROM memory cell relies on charge exchange between the substrate and the floating-gate electrode, considerable stress is placed on the tunnel oxide underlying the floating-gate electrode. The charge-induced stress in the tunnel oxide can cause charge-trapping sites to form within the tunnel oxide. The formation of these charge-trapping sites is undesirable because, once formed, electrical current can leak through the tunnel oxide layer from the floating-gate electrode to the substrate. When charge leaks off the floating-gate electrode a data error occurs in the EEPROM memory cell.
One solution to the tunnel oxide leakage problem is to form thicker oxide layers within the EEPROM device. By providing more oxide, the formation of a small number of charged trapping sites can be tolerated without deleterious current leakage in the device. While fabricating the oxide layers to greater thicknesses reduce charge leakage problems, the thicker oxide layers have the undesirable side effect of increasing the overall size of the EEPROM memory cell.
A need therefore exists for a way to improve data retention in memory cells without increasing their size.
SUMMARY
The present invention, roughly described, pertains to a method for forming a three transistor zero power memory cell including a p-channel sense transistor, an n-channel write transistor, and an n-channel sense transistor. In one aspect, the method includes: implanting a p-type impurity into a p-type substrate in which a n-channel high voltage transistor will be formed; implanting an n-type impurity into an n-type well in a p-type substrate in which a p-channel high voltage transistor will be formed; forming a mask to allow implants to occur to p-channel devices; performing a series of n-type dopant implants into the substrate where the p-channel transistors will be formed; growing a high voltage gate oxide; forming a mask to allow implants to occur to n-channel devices, said mask blocking implants to said n-channel sense transistor; and performing a series of p-type implants into the substrate where the n-channel devices will be formed.
In a further aspect, the invention comprises a memory cell. The memory cell may include a first NMOS transistor having a source, drain and gate, and a first PMOS transistor. The first PMOS transistor has a source, drain and gate, and the gate of the PMOS transistor is coupled to a floating gate region and said gate of said first NMOS transistor. In addition, the drain of said PMOS transistor is coupled to the drain of said first NMOS transistor. The memory cell further includes a second NMOS transistor, having a source coupled to a tunnel capacitor, the output of the tunnel capacitor coupled to the floating gate region. In a further aspect, the first NMOS transistor and first PMOS transistor each include a three-implant channel region, and wherein the second NMOS transistor further includes a two-implant channel region.
These and other aspects of the present invention will appear more clearly from the following description in which the preferred embodiment of the invention has been set forth in conjunction with the drawings.


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