Zero power latchup suppression circuit

Details Zero power latchup suppression circuit Zero power latchup suppression circuit

1993-11-24

1997-06-03

Martin, David S.

Electrical transmission or interconnection systems

Plural supply circuits or sources

Connecting or disconnecting

307 66, 323908, 365229, H02J 100

Patent

active

056357745

ABSTRACT:
A zero power circuit includes an upper power supply voltage pad, battery pad, a power control circuit, and a suppression circuit. The power control circuit provides power to the zero power circuit by switching between the battery pad and the upper power supply voltage pad. The suppression circuit is connected in series between the power control circuit and the battery pad. The suppression circuit includes a resistor connected in series between the battery pad and the power control circuit, wherein current flowing through the transistor during a latch condition causes the voltage to drop across the resistor, suppressing the latchup condition to the battery pad. The suppression circuit also includes a transistor connected in parallel with the resistor, the transistor having a gate, wherein a first signal applied to the gate turns off the transistor and a second signal applied to the gate turns on the transistor, wherein the resistor is shorted when the transistor is turned on.

REFERENCES:
patent: 4716511 (1987-12-01), Masaki
patent: 4908790 (1990-03-01), Little et al.
patent: 4984211 (1991-01-01), Tran
patent: 5099453 (1992-03-01), Steele
patent: 5148042 (1992-09-01), Nakazoe
patent: 5241508 (1993-08-01), Berenguel
patent: 5278798 (1994-01-01), Miyawaki
patent: 5306961 (1994-04-01), Leo
patent: 5307318 (1994-04-01), Nemoto
patent: 5315549 (1994-05-01), Scherpenberg et al.

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