Zero power high speed configuration memory

Details Zero power high speed configuration memory Zero power high speed configuration memory

1997-11-25

1999-08-31

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365221, 365239, G11C 800

Patent

active

059462671

ABSTRACT:
A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.

REFERENCES:
patent: 5086388 (1992-02-01), Matoba et al.
patent: 5473577 (1995-12-01), Miyake et al.

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