Synchronous semiconductor memory device capable of reducing dela

Details Synchronous semiconductor memory device capable of reducing dela Synchronous semiconductor memory device capable of reducing dela

1997-10-07

1999-08-31

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36523003, G11C 800

Patent

active

059462663

ABSTRACT:
In a synchronous dynamic random access memory (SDRAM), one bank A is divided into banks A0 and A1, and two sets of writing-related circuits are arranged corresponding to each memory cell array bank and are capable of performing writing operation substantially independently. The first and second bits of write data applied successively from the outside world are applied alternately to write registers. Since the I/O line pair is connected to the selected memory cells in respective memory cell array banks after incorporation of the second bit data to be written is completed, the potential levels of the corresponding I/O line pair always change to the corresponding potential levels from the initial state in writing the first and second bit data.

REFERENCES:
patent: 5404338 (1995-04-01), Murai et al.
patent: 5485426 (1996-01-01), Lee et al.
patent: 5592434 (1997-01-01), Iwamoto et al.
"16Mbit Synchronous DRAM with 125Mbyte/sec Data Rate", Choi et al., 1993 Symposium on VLSI Circuits, pp. 65-66.
"A 150-MHz 4-Bank 64M-bit SDRAM with Address . . . ", Kodama et al., 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 81-82.
"A 180MHz Multiple-registered DRAM for low-cost . . . ", Iwamoto et al., IEEE 1994 Custom Integrated Circuits Conference, pp. 591-594.

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