Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2002-02-12
2003-09-09
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S200000, C365S230080, C365S189110, C365S096000, C365S094000, C365S102000, C327S525000, C327S526000, C716S030000
Reexamination Certificate
active
06618311
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to fuse enabled redundancy memory, and more particularly to zero power fuse sensing circuitry for redundancy applications in computer memories.
2. Description of the Related Art
Currently, semiconductor devices are becoming faster and highly integrated with the development of refining techniques, including semiconductor memory devices. However, if one memory cell of a memory device is defective, the entire memory device may no longer operate properly. Moreover, with the higher integration of semiconductor memory devices, the frequency of defects in memory cells is further increased. Such defective memory cells deteriorate the functionality of the memory device, and have become one of the main factors that lower the yield of semiconductor memory devices.
To address this issue, redundancy systems have been developed that improve yield by replacing defective cells with redundant cells.
FIG. 1
is a block diagram showing prior art redundancy system
100
for replacing defective memory cells with redundant memory cells. The redundancy system
100
includes a master fuse
102
connected to a fuse box
104
, which controls access to redundant memory
106
. The redundancy system
100
drives spare redundancy memory cell blocks arranged in columns and rows, and selects a redundant memory cell in the redundancy memory
106
to replace the defective cell. Generally, when a defective cell is addressed, a fuse in the fuse box
104
, which is connected to the defective column and/or row, is cut such that a redundant column and/or row within the redundancy memory
106
is selected instead of the defective column and/or row.
To avoid unnecessary power consumption, the redundancy system
100
includes a master fuse
102
, which controls power flow to the fuse box
104
. When the redundant memory cells within redundant memory
106
are not in use, the master fuse
102
remains intact and prevents current flow to the fuse box
104
. In this manner, the fuses in the fuse box
104
do not bum power when none of the memory cells within the redundant memory
106
are in use. Conversely, when the redundant memory cells within redundant memory
106
are needed to replace defective memory cells, the master fuse
102
is cut to allow current flow to the fuse box
104
. However, when the master fuse
102
is cut, current is provided to all the fuses in the fuse box
104
. As a result, fuses not being used to redirect memory addresses begin to bum power.
FIG. 2
is a schematic diagram showing a prior art fuse state sensing circuit
200
. The prior art fuse state sensing circuit
200
includes an enable transistor
202
having a gate coupled to an enable signal
204
, a first terminal coupled to V
DD
, and a second terminal coupled to a fuse
206
. The second terminal is also coupled to a buffer
208
, which provides an output signal
210
for the fuse state sensing circuit
200
.
The enable signal
204
is utilized to indicate whether the fuses in the fuse box are being used, and as such, whether current should be provided to the fuse state sensing circuit
200
. In particular, when the master fuse is blown, the enable signal
204
provides a low signal to the enable transistor
202
, thus turning on the enable transistor
202
and allowing current to flow from the first terminal to the second terminal. This current flows to ground when the fuse
206
is intact, and as a result the buffer outputs a high on the output signal
210
. When the fuse
206
is blown indicating the corresponding redundant memory is in use, node
212
remains high and the buffer
208
outputs a low on the output signal
210
.
Unfortunately, the prior art fuse state sensing circuit
200
burns power when the fuse
106
is intact. Hence, the prior art fuse state sensing circuit
200
burns power when the corresponding redundant memory is not in use. As a result, when the master fuse is blown, all intact fuses in the corresponding fuse box burn power, which can create problems in low power applications.
In view of the foregoing, there is a need for low power fuse sensing circuitry. The fuse sensing circuitry should not burn power when the corresponding redundant memory blocks are not in use. Moreover, the fuse sensing circuitry should avoid using a master fuse, which burns additional power.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a zero power fuse sensing circuit for use in redundant memory applications. In one embodiment, a fuse state sensing circuit is disclosed that senses the state of a fuse, which is coupled between ground rail and a fuse state sensing node. The fuse state sensing node indicates a state of the fuse when rail voltage is provided to the fuse state sensing circuit. In addition, a capacitive element is included that is coupled to the fuse state sensing node. The capacitive element is capable of providing a first amount of current to the fuse state sensing node when an initial voltage is supplied to the rail voltage. The capacitive element is further configured to stop supplying the first amount of current upon reaching a threshold voltage of the capacitive element. The fuse state sensing circuit further includes a keeper latch circuit that is coupled to the fuse state sensing node in parallel with the capacitive element. The keeper latch circuit is capable of latching the state of the fuse state sensing node. In addition, the keeper latch circuit stops supplying current to the fuse state sensing node when the rail voltage is reached if the fuse is intact. Also, when the rail voltage reaches a predetermined voltage and the fuse is blown, the keeper latch circuit continues to supply current to the fuse state sensing node.
A further fuse state sensing circuit is disclosed in further embodiment of the present invention. This embodiment includes a fuse that is coupled between ground rail and a fuse state sensing node. The fuse state sensing node indicates a state of the fuse when rail voltage is provided to the fuse state sensing circuit. In addition, a capacitive element is included that is coupled to the fuse state sensing node. The capacitive element is capable of providing a first amount of current to the fuse state sensing node when an initial voltage is supplied to the rail voltage. The capacitive element is further configured to stop supplying the first amount of current upon reaching a threshold voltage of the capacitive element. The fuse state sensing circuit also includes a pull up circuit that is coupled to the fuse state sensing node in parallel with the capacitive element. The pull up circuit stops supplying current to the fuse state sensing node when the rail voltage reaches a predetermined value if the fuse is intact. In addition, as above, the pull up circuit continues to supply current to the fuse state sensing node when the rail voltage is reached and the fuse is blown.
In yet a further embodiment of the present invention, a method for sensing a fuse state for a redundancy application is disclosed. An initial voltage is supplied to the rail voltage of the circuit. Also, an initial current is provided to a fuse state sensing node utilizing a capacitive element. As above, the capacitive element ceases to provide current to the fuse state sensing node upon reaching a predetermined voltage threshold. Additional current is supplied to the fuse state sensing node when the fuse is blown utilizing a pull up circuit and a keeper latch circuit. However, when the fuse is intact, the pull up circuit and a keeper latch circuit stop supplying current to the fuse state sensing node.
Advantageously, using the embodiments of the present invention, intact fuses within the fuse box do not burn power. By controlling current flow, embodiments of the present invention prevent current flow across intact fuses during normal memory operation. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompa
Artisan Components Inc.
Martine & Penilla LLP
Tran Andrew Q.
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