Zero power, electrically alterable, nonvolatile latch

Details Zero power, electrically alterable, nonvolatile latch Zero power, electrically alterable, nonvolatile latch

1988-01-28

1989-08-15

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365185, 365154, 36518905, 365227, G11C 1140, G11C 1300

Patent

active

048581852

ABSTRACT:
A compact, nonvolatile, zero static power, electrically alterable, bistable CMOS latch device is fabricated with single layer of polysilicon. The single polysilicon layer forms the floating gates of the nonvolatile elements of the device. The control gates are formed in the substrate by buried N+ diffusions and are separated from their respective floating gates by a thin oxide dielectric. The circuit can be designed to power-up in a preferred mode even before any programming operation has been performed on it. Thereafter, the circuit is available to be programmed to either of its two stable states. After the programming operation is completed and the circuit is latched to one of its two stable states, the fields across the thin oxide dielectrics are minimal and virtually no read disturb condition exist. Thus, the latch also offers excellent data retention characteristics.

REFERENCES:
patent: 4132904 (1979-01-01), Harari
patent: 4328565 (1982-05-01), Harari
patent: 4409723 (1983-10-01), Harari
patent: 4486769 (1984-12-01), Simko
patent: 4571704 (1986-02-01), Bohac, Jr.
patent: 4599706 (1986-07-01), Guterman
patent: 4628487 (1986-12-01), Smayling
patent: 4695979 (1987-09-01), Tuvell et al.

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