Zero-overhead loop operation in microprocessor having...

Details Zero-overhead loop operation in microprocessor having... Zero-overhead loop operation in microprocessor having...

2007-01-02

2007-01-02

Fleming, Fritz (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S239000

Reexamination Certificate

active

10396063

ABSTRACT:
A loop instruction, at least one target instruction, and an associated trigger address are cached during loop entry. During each loop iteration, the processor predicts whether the loop will be taken or not-taken in a subsequent iteration. When pre-fetch of the cached loop instruction is subsequently detected (i.e., by comparing the trigger address with the current program counter value), the loop taken
ot-taken prediction is used to fetch either loop body instructions (when predicted taken) or fall-through instructions (when predicted not-taken). The cached loop instruction is then executed and the loop taken
ot-taken prediction is verified using a dedicated loop execution circuit while a penultimate loop body instruction is executed in the processor execution stage (pipeline). When a previous loop taken prediction is verified, the cached target instruction is executed, and then the fetched loop body instructions are executed. When a loop not-taken prediction is verified, the fetched fall-through instructions are executed.

REFERENCES:
patent: 5734881 (1998-03-01), White et al.
patent: 6076159 (2000-06-01), Fleck et al.
patent: 6085315 (2000-07-01), Fleck et al.
patent: 6477639 (2002-11-01), Krishnan et al.
Intel Architecture Software Devloper's Manual, 1997, Intel Co., vol. 2, p. 278-279.

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