Zero interface polysilicon to polysilicon gate for flash memory

Details Zero interface polysilicon to polysilicon gate for flash memory Zero interface polysilicon to polysilicon gate for flash memory

2011-01-04

2011-01-04

Jackson, Jr., Jerome (Department: 2815)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C257S315000, C257SE21209, C438S257000

Reexamination Certificate

active

07863175

ABSTRACT:
A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a flash memory device. An exemplary method can include removing an oxide on a surface of a first poly layer and forming a second poly layer on the first poly layer in a same processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.

REFERENCES:
patent: 5972804 (1999-10-01), Tobin et al.
patent: 6436760 (2002-08-01), Wong et al.
Abdul-Rahim et al “Improved control of polysilicon emitter . . . cluster tool” 1997 IEEE 0-7803-4135-X/97/.

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