Zero hold time circuit for high speed bus applications

Details Zero hold time circuit for high speed bus applications Zero hold time circuit for high speed bus applications

1998-09-30

2002-05-28

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C326S049000

Reexamination Certificate

active

06397374

ABSTRACT:

1.0 FIELD OF THE INVENTION
The present invention relates to CMOS input cells and, more specifically, to the implementation of a zero hold time CMOS input cell which utilizes a programmable delay line. This input cell is suitable for use in many high speed data bus applications.
2.0 DESCRIPTION OF THE RELATED ART
An edge triggered D flip-flop (or D flop) is a well known device which captures the logic state of a data input signal on the rising (or falling) edge of a clock input signal. In practice, integrated circuits (ICs) commonly use D flops to capture input data from an external bus.
FIG. 1
shows a simplified circuit diagram which illustrates a portion of a conventional integrated circuit
100
. As shown in
FIG. 1
, circuit
100
includes a D flop
110
which is located in the core of circuit
100
, and an input data cell
112
. Input data cell
112
includes an input data pin
116
, which receives a data input signal DATA from an external data bus
118
. Input data pin
116
, in turn, supplies the DATA signal to a CMOS/TTL compatible data input buffer
114
, whose output directly drives the D input of flop
110
.
Similarly, circuit
100
also includes an input clock cell
120
. Input clock cell
120
includes a clock input pin
124
, which receives a clock input signal CLK from an external source. Clock input pin
124
, in turn, supplies the CLK signal to a CMOS/TTL compatible clock input buffer
122
, whose output directly drives the CLK input of flop
110
.
As shown in
FIG. 1
, the DATA signal from external data bus
118
must be captured (i.e. latched) by flop
110
. In order for this to occur, the specified minimum setup and hold times for flop
110
must be met. In general, these minimum setup and hold times can be positive, negative or zero. Because setup and hold times are signed numbers, they are, by convention, interpreted as follows. For a rising edge triggered flop, a positive setup time indicates that the data on the flop D pin must change state before the clock rises on the flop CLK pin. Conversely, a negative flop setup time allows the data on the flop D pin to change state after the clock rises on the flop CLK pin.
Similarly, for a rising edge triggered flop, a positive hold time indicates that the data on the flop D pin must change state after the clock rises on the flop CLK pin. Conversely, a negative flop hold time allows the data on the flop D pin to change state before the clock rises on the flop CLK pin.
For example, if the specified minimum setup time for flop
110
is +1 ns, flop
110
will capture the correct data if it is presented with a setup time of +1 ns, +2 ns or +3 ns. Flop
110
will not capture the correct data, however, if it is presented with a setup time of −1 ns, 0 ns or +0.5 ns.
Similarly, if the specified minimum hold time for flop
110
is −0.5 ns, flop
110
will capture the correct data if it is presented with a hold time of −0.5 ns, 0 ns or +1 ns. Flop
110
will not capture the correct data, however, if it is presented with a hold time of −3 ns, −2 ns or −1 ns.
From the foregoing examples, it can be seen that the specified minimum setup and hold times for flop
110
will be met if the following statement is true: the setup and hold times presented to flop
110
must be arithmetically greater than or equal to its specified minimum setup and hold times.
2.1 Zero Hold Time Bus Conditions
One of the problems associated with capturing data from a high speed synchronous data bus, such as the PCI bus, is that data can change state at exactly the same time that the clock rises (assuming a rising edge clock reference). Thus ICs which are connected to high speed synchronous data buses are often required to operate with zero hold time at their data bus input pins, relative to their clock input pin.
Referring to
FIG. 1
, in order to determine whether or not the minimum setup and hold requirements of flop
110
are being met, the following parameters must be examined: the relative timing of the input signals DATA and CLK, and the delays imposed by data input buffer
114
and clock input buffer
122
. These parameters will be examined in the following paragraphs.
As shown in
FIG. 1
, the signal path to the D input of flop
110
goes through data input buffer
114
, which has a relatively low fanout (only one in this PCI bus example). However, the signal path to the CLK input of flop
110
goes through clock input buffer
122
, which has a relatively high fanout (
49
in this PCI example). Due to this difference in fanout, the load capacitance on data input buffer
114
will be far less than the load capacitance on clock input buffer
122
. This difference in load capacitance implies that the delay through data input buffer
114
will be far less than the delay through clock input buffer
122
. (Note: In most high speed bus applications it is not possible to speed up the clock input buffer to the point where its delay is less than or equal to the delay through the data input buffer).
From the above discussion it can be seen that the delay from data input pin
116
to the D input of flop
110
will usually be less than the delay from clock input pin
124
to the CLK input of flop
110
. Hence, when the clock and data signals have a zero hold time relationship at the chip input pins (i.e. on the bus), the hold time imposed on flop
110
can be highly negative, causing a hold time violation. This hold time violation can cause the wrong bus data to be captured, resulting in a system malfunction.
FIG. 2A
shows a timing diagram which illustrates the hold time violation described in the preceding paragraph. In this example it is assumed that flop
110
in
FIG. 1
has a specified minimum hold time of −0.5 ns. In accordance with the foregoing discussion, it is also assumed that the delay through data input buffer
114
in
FIG. 1
is 1 ns, and that the delay through clock buffer
122
in
FIG. 1
is 3 ns.
As shown by waveforms A and B in
FIG. 2A
, the input signals CLK and DATA both change state at exactly the same time (0 ns). Thus the correct data which must be captured by flop
110
in
FIG. 1
is designated as ‘D1’ in FIG.
2
A. However, because the delay through clock buffer
122
in
FIG. 1
is 3 ns, the CLK pin of flop
110
will not go high until 3 ns, as shown by waveform C in FIG.
2
A. Similarly, because the delay through data buffer
114
in
FIG. 1
is only 1 ns, the D pin of flop
110
will change state at 1 ns, as shown by waveform D in FIG.
2
A. Thus, when comparing waveforms C and D in
FIG. 2A
, it can be seen that the hold time presented to flop
110
is equal to −2 ns. Since the minimum hold time for flop
110
is −0.5 ns, flop
110
has a hold violation of 1.5 ns (absolute value). Thus flop
110
will not capture the correct data ‘D1’; it will instead capture the wrong data ‘D2’.
The above hold time violation can be corrected by modifying the circuit shown in FIG.
1
. Referring to
FIG. 3
, circuit
300
is similar to circuit
100
shown in
FIG. 1
, and, as a result, uses the same reference numerals to designate structures which are common to both circuits.
The circuit shown in
FIG. 3
illustrates a portion of a conventional integrated circuit
300
. As shown in
FIG. 3
, the hold time violation for flop
110
can be corrected by adding a delay circuit
310
to input data cell
112
. Thus, as shown by the waveforms in
FIG. 2B
, if the added delay is equal to at least 1.5 ns, the hold time violation for flop
110
will disappear (i.e. the imposed hold time will increase from −2 ns to −0.5 ns).
Referring to
FIG. 3
, if the added delay
310
is too short, the zero hold time requirement will not be met. Conversely, if the added delay is too long, the flop hold time will be more than sufficient, but the flop setup time may be decreased to the point where a setup violation occurs. (This assumes that the clock period, t
CLK
, and the maximum logic chain delay, t
LOGIC
, do not change—i.e. t
CLK
=t
SETUP
+t
HOLD
+t

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