Zero delay regenerative circuit for noise suppression on a compu

Details Zero delay regenerative circuit for noise suppression on a compu Zero delay regenerative circuit for noise suppression on a compu

1997-08-29

1999-11-30

Tokar, Michael

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

326 30, 326 28, 326 90, 326 86, 326 93, H03K 19003, H03K 190175, H03K 1900

Patent

active

059949180

ABSTRACT:
A novel zero delay regenerative circuit is presented. The circuit, when connected to a data bus, suppresses noise, reduces time delay and provides sharper edge rates. A first input of a NOR gate is connected to an input node. A second input of the NOR gate is connected to the precharge clock of the bus. The output of the NOR gate is connected to the gate terminate of a field-effect transistor (FET). With the drain terminal connected to ground, the source terminal of the FET is connected to an output node. The input and output nodes are shorted together.

REFERENCES:
patent: 3946251 (1976-03-01), Kawagoe
patent: 5166561 (1992-11-01), Okura
patent: 5179299 (1993-01-01), Tipon
patent: 5440182 (1995-08-01), Dobbelaere
patent: 5546016 (1996-08-01), Allen
Mark N. Horenstein, Microelectronic Circuit & Devices, pp. 753-755, 1990.

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