Zero-delay buffer circuit for a spread spectrum clock system...

Details Zero-delay buffer circuit for a spread spectrum clock system... Zero-delay buffer circuit for a spread spectrum clock system...

2006-01-31

2006-01-31

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000, C375S373000, C375S375000, C327S158000

Reexamination Certificate

active

06993109

ABSTRACT:
A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

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Michael T. Zhang, “Notes on SSC and Its Timing Impacts” Intel, Rev 1.0, Feb. 1998, pp. 1-8

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