Zero cycle penalty in selecting instructions in prefetch...

Details Zero cycle penalty in selecting instructions in prefetch... Zero cycle penalty in selecting instructions in prefetch...

2006-04-18

2006-04-18

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Hashing

C711S125000, C711S137000, C711S220000, C712S205000, C712S207000, C712S237000

Reexamination Certificate

active

07032097

ABSTRACT:
A method and processor for selecting instructions in a prefetch buffer in the event of a miss in an instruction cache with a zero cycle penalty. A first, second and third hash may be performed on an address retrieved from a program counter. The first hashed address may be used to index into the instruction cache. The second hashed address may be used to index into the prefetch buffer. If the value stored in the indexed entry in an effective address array of the instruction cache does not equal the value of the third hash of the address (an instruction cache miss), then the instructions in the indexed entry in the prefetch buffer are selected. In this manner, instructions may be selected in the prefetch buffer in the event of a miss in the instruction cache with a zero cycle penalty.

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Jouppi, Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, 1990, IEEE, pp 364-373.

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