Zero clock skew computer module

Details Zero clock skew computer module Zero clock skew computer module

1999-09-09

2003-07-08

Lee, Thomas (Department: 2185)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S500000, C713S503000, C713S600000

Reexamination Certificate

active

06591372

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to timing of chips on a computer board, and more specifically to timing of memory chips on a memory board.
BACKGROUND OF THE INVENTION
A computer board receives a timing pulse from a wire carrying a train of clock pulses. The wire is oftentimes a conductor associated with a bus with which the computer board is connected, oftentimes with the computer board being plugged into a connector. The connector is oftentimes an integral part of the bus. The wire, or bus conductor, is often a conducting trace made as part of the motherboard of the computer. The conducting traces of the bus may be made on the motherboard of the computer by etching, etc.
A computer board normally has pins along at least one side of the board. The pins make contact with conductors within a connector of the bus. The connector is oftentimes made integral with the etched traces of the bus. The etched traces of the bus and the connectors to the bus are then an integral part of the motherboard of the computer. When the computer board is plugged into the connector, the clock pulses carried by the clock trace of the bus are received by a pin along the edge of the computer board, the computer board clock pin. Timing of clock pulses at memory chips on memory boards of a computer is critical in order to have memory read and write operations work without failures. Further, computer boards which serve as memory boards have chips which serve as buffers and which serve as registers. Timing of pulses at register chips, buffer chips, and the memory chips are critical to proper functioning of memory read and write operations in the computer. The following discussion applies to all types of computer boards. However, the discussion will focus on memory boards as an example, since clock pulse timing is critical on memory boards.
The clock input pin to a memory board is referred to as the“memory board clock pin”. The memory board clock pin must be connected to the various chips mounted on the memory board. This connection is oftentimes made by traces, or conducting paths etched into the computer board, or into the memory board. Variations in length of the traces etched into the memory board cause variations in the time difference between arrival of a clock pulse at the memory board clock pin, and arrival of a clock pulse at a chip mounted on the memory board. Propagation speeds of 100 to 200 picoseconds per inch along a trace in a memory board are typical. Thus a ¼ inch difference in path length from a clock pin to a first chip and from the clock pin to a second chip can result in a timing difference of from 25 picoseconds to 50 picoseconds. Such timing differences are significant in the operation of computers operating with clocks of several hundred megahertz, and must be eliminated or accounted for in the computer system design. For example, a computer operating with a clock speed of 100 megahertz on the bus has a cycle time of 10**(−8) seconds, or 10,000 picoseconds. In the event that random timing errors between memory chips of 25 to 50 picoseconds are introduced by a manufacturer into a system operating with a bus clock speed of 10,000 picoseconds per cycle (100 megahertz), or for example, 5,000 picoseconds per cycle (500 megahertz), the timing errors may be sufficiently large to cause memory store and read operations to fail.
It is standard engineering practice to include a phase lock loop (PLL) chip on a memory board to adjust timing of clock pulses reaching memory chips on the board. The input of the PLL chip is driven by a clock pulse received from the memory board clock pin. The output of the PLL chip is connected by traces which all have the same length to a plurality of memory chips on the memory board. For example, a memory board with eight memory chips will have traces from the output pin of the PLL chip to each of the input clock pins of each memory chip. And the traces from the PLL output pin to the input clock pins of the memory chips are typically designed to be the same length. Having the traces the same length insures that the clock pulses reach each memory chip at the same time, to within any variation in trace length introduced by the manufacturing process. Variation in trace length introduced by a particular vendor's manufacturing processes is usually insignificant.
A timing difference between the arrival time of a clock pulse at the clock input pin of the PLL chip and the time that a pulse is output on the output pin of the PLL chip is adjusted by the length of a feedback path. The feedback path typically originates at a feedback origin pin, and terminates on a feedback termination pin of the PLL chip. It is standard engineering practice to adjust the length of the feedback path, and thus the delay of the output pulse of the PLL chip, so that clock pulses reach the memory chips at a fixed time relative to the arrival time of the clock pulse at the input pin of the PLL chip. For example, the feedback loop is normally adjusted to provide a fixed timing relationship of the clock pulse at the memory chip to the time that a corresponding clock pulse reaches the input pin of the PLL chip.
The length of the trace from the clock pin of the memory board to the clock input pin of the PLL chip determines the delay from the arrival time of the clock pulse at the bus connector into which the memory board is plugged, and the arrival time of the pulse at the PLL chip. One vendor of memory boards may make this trace from the memory board clock pin to the PLL clock input pin one length, and another vendor may make this trace another length. The variation in length of the trace from the memory board clock pin to the PLL clock input pin from one vendor to another vendor introduces delay variation between vendors for the arrival time of clock pulses at memory chips. Thus, if a bus of a computer is populated with memory boards made by different vendors, the clock pulses may reach the memory chips on the various memory boards at different times. The time differences are reckoned by the pulse propagation velocity along a board trace combined with the length differences, and propagation velocities may be between, for example, 100 picoseconds per inch and 200 picoseconds per inch. Typical differences in vendor's trace lengths between the board clock pin and the PLL input pin may be sufficient for the timing variations at the memory chips to cause memory read or write errors.
There is needed a way to eliminate variation of clock pulse timing at memory chips caused by different vendors using different trace lengths, so that a bus in a computer may be populated with memory boards made by different vendors.
SUMMARY OF THE INVENTION
The invention adjusts the length of the feedback trace of the phase lock loop of he PLL chip so that the timing of clock pulses at memory chips is measured relative to he arrival time of a clock pulse at the memory board clock pin. This adjustment of the length of the feedback loop accounts for the length of the trace from the memory board clock pin to the PLL clock input pin. This adjustment of the length of the feedback loop removes uncertainty between vendors in the arrival time of clock pulses at the memory chips, relative to arrival time of clock pulses at the memory board clock pin. A system designer then has control of the arrival time of a pulse at a memory chip clock pin by adjustment of the arrival time of the clock pulse at the memory board clock pin, and no variation is introduced between vendors who adopt the invention in their design of memory boards.


REFERENCES:
patent: 5257294 (1993-10-01), Pinto et al.
patent: 5347232 (1994-09-01), Nishimichi
patent: 6003118 (1999-12-01), Chen
patent: 6047383 (2000-04-01), Self et al.
patent: 6112308 (2000-08-01), Self et al.

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