Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification
Reexamination Certificate
2011-04-19
2011-04-19
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Analysis and verification
C716S052000, C716S053000, C716S054000, C716S055000, C716S056000
Reexamination Certificate
active
07930655
ABSTRACT:
A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
REFERENCES:
patent: 2001/0031407 (2001-10-01), Okino et al.
Abercrombie David A.
Behkami Nima A.
Desu ChandraSekhar
Sturtevant David J.
Whitefield Bruce J.
Dinh Paul
LSI Corporation
Luedeka Neely & Graham P.C.
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