Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-04-27
2002-12-17
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S121000
Reexamination Certificate
active
06496958
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to yield prediction and production control and more particularly, to a method for determining yield for semiconductor fabrication processes.
2. Description of the Related Art
A common standard exists in the semiconductor industry where wafers are inspected at various times by optical and other inspection tools during production. As a result, a process engineer obtains a number of defects per wafer, x and y coordinates of each defect and a set of parameters (different for different tools) specific for each particular defect. Any irregularities, such as structural imperfections, particles, residuals or embedded foreign material are considered as defects. Defect data collected by laser scanning, optical or SEM in-line defect inspections during the production of modern semiconductor devices are comprised of events with absolutely different yield impact. Overall this total count information does not enable the process engineer to assign a yield loss to defects detected at a certain process step.
In-line Statistical Process Control (SPC) is performed after the total defect count is provided by the inspection tool directly, or after yield loss estimations are provided from automated or manual review information (for example, from an optical microscope or SEM). Because high defect counts do not necessarily indicate high yield detraction, the previously described methodology is not an optimized process control. The additional review after yield loss estimations (manual and/or automated) requires additional human resources, extends the process time and postpones information feedback to the process units.
Considering killing probabilities of any of the detected defects (probability p of the defect to kill the entire chip), the total defect count is comprised of events with all values of killing probabilities between 0 and 1. The count information on its own (even including further characterization of each single defect by optical microscopes, scanning electron microscopes (SEM), atomic force microscopes (AFM), energy-dispersive X-ray spectroscopy (EDX) (either manual review or automated defect classification)) is not sufficient to assign an accurate number of yield loss to this process part for complex chip designs (e.g., numerous redundancies on memory products). Therefore, this number of yield loss is not a good value to be used for an effective production control. To obtain useful yield impact information, it is indispensable to correlate the actual defect data to electrical fails. Waiting for the electrical data, however, delays the feedback to the process units by weeks or months. Therefore, the immediate correct interpretation of the in-line inspection data is essential to approach high productivity.
A real time yield prediction methodology without additional optical review uses historic data for a given process step to calculate one average killing probability for all defects. The detected number of defects or number of defective dies (dies including one or more defects) on a certain wafer is multiplied by this number. As a result, the engineer obtains the number of killed chips. This methodology is only applicable and accurate for single wafers if the wafer contains a normal defect pareto for this process step. The methodology is questionable because excursions in the defect count trend typically do not follow the standard pareto for each layer.
Therefore, a need exists for an optimized control process considering all available information for any single detected defect which may include statistical process or production control for real time yield impact information on semiconductor devices. A further need exists for an automated method which does not require manual defect classification.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method, which may be implemented by employing a program storage device, for determining yield loss for a device includes the steps of determining killing probabilities corresponding to values of inspection parameters based on historic inspection information, determining defects on the device, classifying the defects according to the inspection parameters, the defects adopting the killing probabilities associated with the same values of the inspection parameters and calculating a predicted yield loss based on the defects and the adopted killing probabilities.
In other methods, which may be implemented by employing a program storage device, the step of determining defects on the device may include the step of inspecting the device using inspection tools. The step of classifying the defects may include the steps of determining defect inspection parameters used to determine each defect, finding corresponding values of the defect inspection parameters with the values of the inspection parameters determined based on historic information, and associating the killing probability of the values of the inspection parameters determined based on historic information with each defect having the corresponding values. The method may further include the step of calculating a predicted yield loss for each of a plurality of inspection processes. The step of calculating a predicted yield loss for each of a plurality of inspection processes may be performed by calculating the predicted yield loss according to the equation
Δ
Y
k
=
1
-
∏
ij
(
1
-
kp
kij
n
kij
)
where &Dgr;Y
k
is the predicted yield loss for a process k, kp
k
is the adopted killing probability for a defect n
k
and i and j are counters. The method may include the step of calculating an overall predicted yield loss based on the predicted yield loss of the plurality of inspection processes. The step of calculating an overall predicted yield loss based on the predicted yield loss of the plurality of inspection processes may be performed by calculating the overall predicted yield loss according to the equation
Δ
Y
=
1
-
∏
k
(
1
-
Δ
Y
k
)
where &Dgr;Y
k
is the predicted yield loss for a process k and &Dgr;Y is the overall predicted yield loss. The method may include the step of graphically representing the predicted yield loss. The step of classifying the defects may be performed automatically by a machine, such as a computer. This avoids manually inspection and classification. The step of applying statistical process control to the predicted yield loss is preferably included.
Another method, which may be implemented by employing a program storage device, for determining yield loss for semiconductor wafers includes the steps of creating a parametric space defined by values of at least two inspection parameters, assigning killing probabilities corresponding to values of the at least two inspection parameters based on historic inspection information, inspecting the semiconductor device to determine defects on the semiconductor device, and ordering the defects on the semiconductor device by classifying the defects according to the at least two inspection parameters. The classified defects adopt the killing probabilities of the parametric space to which the defects are assigned. The step of calculating a predicted yield loss based on the defects and the adopted killing probabilities is also included.
In other methods, which may be implemented by employing a program storage device, the step of creating a parametric space defined by values of at least two inspection parameters may further include the steps of forming an m-dimensional space by providing m inspection parameters, the m-dimensional space including subspaces, and assigning values of each of the m inspection parameters to each subspace such that each subspace represents one of a given value and a range of values for each of the m inspection parameters. The step of inspecting the semiconductor device to determine defects on the semiconductor device may include the steps of inspecting the semiconductor device using inspection tools, and generating a results file. The
Lammering Herbert
Ollendorf Heinrich
Ott Reinhold
Braden Stanton
Garbowski Leigh Marie
Infineon Technologies Richmond LP
Smith Matthew
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