Yield optimization in router for systematic defects

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

07398485

ABSTRACT:
Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the structural identifiers include wire codes, tags, and/or unique identifiers. Different structural identifiers are established for wires having different widths. Furthermore, the method establishes a weighting factor for each structure-specific mechanism, wherein higher weighting factors are established for structure-specific mechanisms comprising thick wires proximate to multiple thick wires. The method establishes the structural identifiers and the weighting factors for incidence of spacing between single wide lines, double wide lines, and triple wide lines and for incidence of wires above large metal lands. Subsequently, the router settings are modified based on the structural identifiers and the weighting factors to minimize systematic defects.

REFERENCES:
patent: 6927489 (2005-08-01), Yaguchi et al.
patent: 2001/0039644 (2001-11-01), Le Coz
patent: 2004/0163062 (2004-08-01), Chevallier et al.
patent: 2005/0060676 (2005-03-01), Matsumura et al.
patent: 2006/0101355 (2006-05-01), Ciplickas et al.

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