Yield-limiting design-rules-compliant pattern library...

Details Yield-limiting design-rules-compliant pattern library... Yield-limiting design-rules-compliant pattern library...

2005-12-30

2008-11-25

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07458060

ABSTRACT:
A method and system are provided for analyzing process window compliance of an integrated circuit design. Aspects of the present invention include identifying layout pattern configurations that have process windows that fail to meet respective local performance specifications; searching for any layout pattern configurations in a design that substantially match any of the identified layout pattern configurations; and modifying any matching layout pattern configurations found in the design to make the layout pattern configurations compliant with their respective process windows.

REFERENCES:
patent: 6553559 (2003-04-01), Liebmann et al.
patent: 7194725 (2007-03-01), Lukanc et al.
patent: 7266798 (2007-09-01), Mansfield et al.
patent: 2005/0050512 (2005-03-01), Kochan et al.
patent: 2006/0273266 (2006-12-01), Preil et al.

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