Yield improvement through probe-based cache size reduction

Details Yield improvement through probe-based cache size reduction Yield improvement through probe-based cache size reduction

2005-07-12

2005-07-12

Torres, Joseph D. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S718000, C714S721000, C714S723000, C365S200000, C365S201000

Reexamination Certificate

active

06918071

ABSTRACT:
A multiple-way cache memory having a plurality of cache blocks and associated tag arrays includes a select circuit that stores way select values for each cache block. The way select values selectively disable one or more cache blocks from participating in cache operations by forcing tag comparisons associated with the disabled cache blocks to a mismatch condition so that the disabled cache blocks will not be selected to provide output data. The remaining enabled cache blocks may be operated as a less-associative cache memory without requiring cache addressing modifications.

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Array Word Redundancy Scheme, IBM Technical Disclosure Bulletin, Aug. 1982, vol. 55, Issue 3A, pp. 989-992.

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