Yield improvement of dual damascene fabrication through...

Details Yield improvement of dual damascene fabrication through... Yield improvement of dual damascene fabrication through...

2000-03-09

2002-10-08

Sherry, Michael (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S637000, C438S694000, C438S738000, C438S745000

Reexamination Certificate

active

06461955

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of forming interconnect layers in integrated circuits and more specifically to dual damascene interconnect processes.
BACKGROUND OF THE INVENTION
As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects. Unfortunately, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.
In a conventional interconnect process, the aluminum (and any barrier metals) are deposited, patterned, and etched to form the interconnect lines. Then, an interlevel dielectric (ILD) is deposited and planarized. In a damascene process, the ILD is formed first. The ILD is then oatterned and etched. The metal is then deposited over the structure and then chemically-mechanically polished to remove the metal from over the ILD, leaving metal interconnect lines. A metal etch is thereby avoided.
One prior art damascene process, a dual damascene process, is described with reference to
FIGS. 1A-E
. Referring to
FIG. 1A
, a silicon nitride layer
12
is deposited over a semiconductor body
10
. Semiconductor body
10
will have been processed through a first metal interconnect layer. A via level dielectric
14
is deposited over silicon nitride layer
12
. Via dielectric layer
14
comprises FSG (fluorine-doped silicate glass). Another silicon nitride layer
18
is deposited over via level dielectric
14
and a second, trench level dielectric
20
is deposited over silicon nitride layer
18
. A via
22
is then patterned and etched through the trench level dielectric
20
, silicon nitride layer
18
and via level dielectric
14
. Silicon nitride layer
12
is used as an etch stop.
Referring to
FIG. 1B
, a spin-on photoresist
24
is deposited to fill a portion of via
22
with photoresist. The result is approximately 600 Å of resist over dielectric
20
and a thickness of ~2000-2500 Å within the via
22
. Photoresist
24
protects via
22
during the subsequent trench etch. Next, the trench,pattern
26
is formed on the. structure as shown in FIG.
1
C. Trench pattern
26
exposes areas of trench level dielectric
20
where the metal interconnect lines are desired.
Referring to
FIG. 1D
, the trench etch to remove portions of FSG layer
20
is performed. Unfortunately, oxide pillars
28
remain due to the slope of via
22
. The remaining portions of photoresist
24
are also removed, as shown in FIG.
1
E. Even after cleanup processing, defects (polymers, etc.) are left in the via
22
. The oxide pillars
28
and defects create problems during subsequent processing. For example, after silicon nitride layer
12
is etched, a barrier metal is typically deposited. It is difficult to ensure that the barrier metal covers oxide pillars
28
. This decreases the process margin. Accordingly, there is a need for a dual damascene process that avoids or minimizes oxide pillars.
SUMMARY OF THE INVENTION
A dual damascene process is disclosed herein. After the via etch, a via protect layer is deposited in the via. The via protect layer comprises a material that has a dry etch rate at least equal to that of the intrametal dielectric (IMD) and a wet etch rate that is approximately 100 times that of the IMD or greater. Exemplary materials include PSG, BPSG, and HSQ. The trench pattern is formed and both the via protect layer and IMD are etched. The remaining portions of the via protect layer are then removed prior to forming the metal layer.
An advantage of the invention is providing a dual damascene process that avoids or minimizes the formation of oxide pillars.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.


REFERENCES:
patent: 5294294 (1994-03-01), Namose
patent: 5736457 (1998-04-01), Zhao
patent: 5970374 (1999-10-01), Teo
patent: 6054380 (2000-08-01), Naik
patent: 6103456 (2000-08-01), Tobben et al.
patent: 6103601 (2000-08-01), Lee et al.
patent: 6153514 (2000-11-01), Wang et al.
patent: 6197696 (2001-03-01), Aoi
patent: 6204166 (2001-03-01), McTeer
patent: 6235628 (2001-05-01), Wang et al.

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