Yield enhancement technique for integrated circuit processing to

Details Yield enhancement technique for integrated circuit processing to Yield enhancement technique for integrated circuit processing to

1996-10-08

1999-11-23

Arroyo, Teresa M.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257760, H01L 29788

Patent

active

059905131

ABSTRACT:
A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H.sub.2 O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein. A second relatively less hydrophilic dielectric layer (such as UTEOS) is then overlaid in at least partial communication with the interlevel dielectric layer and an overlying passivation layer (such as UTEOS) is then applied to the integrated circuit prior to completion of the integrated circuit processing and subsequent packaging operations.

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IBM Technical Disclosure Bulletin, Low Charging Conformal Phosphorous Silicon Glass Passivation Process, Jun. 6, 1995, p. 637.

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