Electronic digital logic circuitry – Exclusive function – With field-effect transistor
Reexamination Certificate
1997-12-30
2004-04-27
Le, Don (Department: 2819)
Electronic digital logic circuitry
Exclusive function
With field-effect transistor
C326S083000
Reexamination Certificate
active
06727728
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an electronic bus and more particularly to a high-speed, digital serial bus interface.
BACKGROUND OF THE INVENTION
The computer and consumer electronic industries are presently developing and implementing a scaleable, flexible, easy to use, low-cost serial digital interface or bus. This bus is known as 1394, which is derived from the IEEE 1394-1995 standard for High Performance Serial Bus, and is hereby incorporated herein by reference. The IEEE 1394 standard defines a backplane physical layer and the serial bus. The bus supports data rates of 100, 200 and 400 Mbits/sec, with 800 and 1600 Mbits/sec planned.
The 1394 bus is digital, which eliminates the need to convert digital data into analog. This provides for better signal integrity. The 1394 bus is a physically small cable (about ⅓ the size of a SCSI cable) that does not require a user to perform a complicated setup. The cable is also hot-pluggable and can support multiple speeds. The 1394 supports daisy chaining and peer-to-peer connections of nodes. Each node typically has three bus connectors or ports, but the 1394 standard provides from one to twenty-seven ports per node.
FIG. 1
shows a cut-away of the 1394 bus cable. Cable
100
includes twisted pairs
110
,
120
, and power wires
130
,
140
. Twisted pair
110
provides bi-directional non-return-to-zero data, and is conventionally known as T
p
A. Twisted pair
120
, conventionally known as T
p
B, provides a strobe signal that accompanies the transmitted data. The strobe signal changes state whenever two consecutive NRZ data bits are the same. This ensures that a transition occurs on either the data or the strobe signal for each bit period. As a result, a clock that transitions each bit period can be derived by combining the data and strobe signal with an exclusive-or function.
FIGS. 2A-C
illustrate the data and strobe signal relationship.
A 1394 protocol includes three layers: physical, link and transaction. Of particular concern to the present invention, the physical layer includes the bus connectors or ports that can number from one to twenty-seven. The physical layer provides arbitration to ensure that only one node at a time is sending data. It also electrically translates signals between the link layer and the 1394 bus.
One problem confronted with data rates of 400 Mbits/sec or greater is jitter. Ideally, the data and the strobe signal transitions are one bit period apart. However, jitter skews these transitions. This jitter then causes erroneous derivation of the clock from the data and the strobe signal. Considering at a 400 Mbits/sec data rate having a 2.5 ns bit period, the clock is a pulse of a relatively short duration (about1.25 nanoseconds). This clock is used to clock other circuitry of the physical layer, particularly flip-flops. Erroneous derivation will obviously propagate throughout the physical layer to interrupt proper data reception.
Another problem associated with the ports of a node (collectively “transceiver port”) is that, in order to get acceptable signal integrity, the twisted pairs should have an approximate nominal 110 ohms impedance. It is therefore desirable to terminate the twisted pairs as close as possible to 110 ohms. Any capacitance across the twisted pair that is not a pure termination causes signal reflections. The 1394 specification requires a differential capacitance of 4 pf on those ports. However, it is practically difficult to meet the requirement because not only are there receiver ports connected to the 1394 bus, but there is also package capacitance and board capacitance.
A further problem with 1394 is that it is a direct coupled system. In other words, there are no coupling capacitors or transformers between port transceivers and the twisted pairs. In fact, the common mode DC level is actually used as a signaling means to signal a port about what speed that they are capable of operating. As a result, the common mode level may have shifted. This is a design problem because potentially the data and strobe port can have a different DC common model level. Furthermore, a biased voltage which is generated at one of the ports and transferred to the other port, and is usually accompanied by a variation. Also, the power cable pair can have up to a 0.5 volt drop in the ground line between the two ports.
All this dictates that a data receiver needs to operate over a wide common mode range. Unfortunately, that range is wider than the range provided from a one device-type input stage in the receiver input of the transceiver (assuming a 3.3V power supply). For example, a NMOS input stage can normally operate from close to the positive voltage supply to about 1.5 volts above the negative voltage supply. That 1.5 volts is directly determined by the threshold voltage of the receiver transistors.
A need exists for a 1394 bus receiver that can properly operate at high data rates. In particular, a 1394 bus receiver is needed that is immune to jitter and can operate over a wide common mode voltage range so that data can be properly received. The present invention meets this need.
SUMMARY OF THE INVENTION
An XOR circuit includes XOR function logic. One advantage of the XOR circuit is that the complements of A and B are not required. The XOR circuit receives an enable signal that disables all the load transistors to eliminate static power dissipation of the XOR circuit and always force the output high when disabled. The output signal of the XOR function logic does not swing rail-to-rail and also has a relatively low drive level. To overcome that, cascade transistor stages are used that have small increments in device sizes, preferably widths, between stages. This allows the fastest rise/fall times at the output of the XOR function logic.
Some applications require jitter tolerance at high data rates. This means that the data and strobe signal transitions can be skewed close together and the data can still be recovered. As a result, an exclusive-or function of the data and strobe to generate the clock must operate at high data rates. Such an exclusive-or function would generate narrow pulses with about a 0.5 nanosecond width. The XOR circuit of the present invention meets this requirement.
Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention and the embodiments thereof, from the claims and from the accompanying drawings in which details of the invention are fully and completely disclosed as a part of this specification.
REFERENCES:
patent: 4477904 (1984-10-01), Thorsrud
patent: 4628216 (1986-12-01), Mazumder
patent: 4710650 (1987-12-01), Shoji
patent: 5138194 (1992-08-01), Yoeli
patent: 5250860 (1993-10-01), Chu et al.
Digital MOS Integrated Circuits; Mohamed I. Elmasry; IEEE Press; 1981; p. 13.
Le Don
LSI Logic Corporation
Maiorana P.C. Christopher P.
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