X.times.Y Bit array multiplier/accumulator circuit

Details X.times.Y Bit array multiplier/accumulator circuit X.times.Y Bit array multiplier/accumulator circuit

1984-05-31

1986-03-11

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

045758123

ABSTRACT:
An X.times.Y bit array multiplier/accumulator circuit is provided for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number, where X and Y are integers. Modified Booth's algorithm is implemented with an array structure which maintains a regular and systematic structure. The array structure uses adders and multiplexers in a predetermined column and row arrangement. Propagation delay is minimized while utilizing the modified Booth's algorithm by using a sum skipping technique and by using inverting logic properties of adders. Sign bit extension is provided by additional logic circuitry and signed/unsigned modes of operation are provided.

REFERENCES:
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4168530 (1979-09-01), Gajski et al.
Pezaris, "A 40-ns 17-Bit by 17-Bit Array Multiplier" IEEE Trans. on Computers, vol. c-20, No. 9, Apr. 1971, pp. 442-447.
Iwamura et al., "A 16-Bit CMOS/SOS Multiplier-Accumlator," 1982 IEEE Int. Conf. ON Ckts., & Computers, Sep. 29, 1982, pp. 151-154.
Hartgring et al., "High-Speed Low-Power Silicon MESFET Parallel Multipliers" J. of Solid State Ckts. vol. SC-17, No. 1, Feb. 1982, pp. 69-73.
Waser, "High-Speed Monolithic Multipliers For Real-Time Digital Signal Processing" Computer Oct. 1978, pp. 19-29.

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