Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2002-07-01
2004-03-23
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S063000, C365S203000, C365S222000
Reexamination Certificate
active
06711078
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to writeback And refresh circuitry for a direct sensed DRAM macro, and more particularly pertains to writeback and refresh circuitry for a direct sensed DRAM macro wherein bitline data is sensed with a primary sense amp (PSA) without a storage means, and then the data is transferred to a latch in a secondary sense amp (SSA) which is common to a group of direct sense memory arrays. A single MDQ master data line is used to first carry the read data as an analog level signal to the SSA, which digitizes the data and then returns the digitized data over the same MDQ global data line as a full-rail digital signal back to PSA and the memory array bitlines.
2. Discussion of the Prior Art
Direct sense memory arrays are memory arrays wherein only the gate of the sense device/transistor is connected to a sensed bitline BL, such that the sense device does not provide any feedback to or alter the signal on the sensed bitline BL. This is in contrast to other prior art nondirect sense memory arrays which include a cross coupled latch wherein typically both the gate and the drain of a sense device/transistor are connected to a sensed bitline BL, and wherein the sense device provides feedback to and alters the signal on the sensed bitline BL.
Direct sense memory arrays typically use a dense and high speed primary sense amp (PSA) which does not latch sensed data during a read operation, and the sensed data is typically directed to an external cache, from which it is written back into the memory array during a refresh operation, which is a very time consuming operation and also requires the use of the external cache which could otherwise be performing other functions in the system. As such, an accessed memory storage cell does not get directly written back, or restored, after a read operation, but rather has an indirect writeback or restore operation.
In a typical nondirect prior art direct sense memory array, data is stored in a latch in the PSA, and is then directly written from the PSA into a memory storage cell. In contrast thereto, in the present invention data is stored in a latch in the secondary direct sense amp (SSA) where it is further amplified and stored as a true digital signal, and is then written directly from the SSA into a memory storage cell.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide writeback and refresh circuitry for a direct sensed DRAM macro wherein bitline data is first sensed with a primary sense amp (PSA) without a storage means, and then the data is transferred to a latch in a secondary sense amp (SSA) which is common to a group of direct sense memory arrays. A single MDQ master data line is used to first carry the read data as an analog level signal to the SSA, which digitizes the data and then returns the digitized data over the same MDQ global data line as a full-rail digital signal back to the PSA and the memory array bitlines.
The present invention provides a circuit for performing a write operation, and a 2-cycle read-write refresh operation to refresh a dynamic eDRAM direct sense memory array. The PSA reads the data and then transfers the data to a shared SSA along a shared MDQ global data line. The SSA converts the analog data to digital data with a resistive isolation device and a latch with weak feedback. The resistive isolation device and a read current supply in the SSA are then shut off, after which a feedback device in the SSA is enabled to pass the inverted and amplified data back to the array cell over the shared MDQ global data line.
The present invention provides a read/writeback mechanism in a destructive read memory array wherein 2-cycles are used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.
REFERENCES:
patent: 5831919 (1998-11-01), Haukness
patent: 5848001 (1998-12-01), Kim
patent: 5926422 (1999-07-01), Haukness
patent: 6072749 (2000-06-01), Nakamura et al.
patent: 6128238 (2000-10-01), Nagai et al.
patent: 6205076 (2001-03-01), Wakayama et al.
Brennan Ciaran J.
Fifield John A.
Stephens Jeremy K.
Storaska Daniel W.
Auduong Gene
International Business Machines - Corporation
Scully Scott Murphy & Presser
Walsh, Esq. Robert A.
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