Writeable shift register lookup table in FPGA with SRAM...

Details Writeable shift register lookup table in FPGA with SRAM... Writeable shift register lookup table in FPGA with SRAM...

2005-12-12

2008-12-09

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

07463056

ABSTRACT:
An FPGA system includes a combined shift register and look up table (LUT) forming a shift register LUT (SRL) that provides data write, reset and shift enable on a cell-by-cell basis. The data write and reset can be performed during FPGA operation without requiring a number of frames or columns of configuration memory cells to be reprogrammed, as with conventional SRAM cells. The shift enable provides for synchronization to facilitate the cell-by-cell write and reset.

REFERENCES:
patent: 5559450 (1996-09-01), Ngai et al.
patent: 5889413 (1999-03-01), Bauer
patent: 6497370 (2002-12-01), Moreaux
patent: 6807123 (2004-10-01), Kaiser et al.

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