Write transaction interleaving

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

Reexamination Certificate

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C710S021000, C710S035000

Reexamination Certificate

active

10862872

ABSTRACT:
A bus master2, 4sends write transactions to a bus slave8which include separate write addresses AW and write data WD. Write transaction identifiers AWID, WID are associated with these write addresses and write data. The bus slave can accept multiple write addresses such that there can be copending write transactions to the same bus slave. The bus slave uses the write transaction identifiers to correlate interleaved write data for the co-pending write transactions with their write addresses.

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The CoreConnect Bus Architecture. International Business Machines Corporation. 1999.
Suzuki et al. A Multimedia-oriented Embedded RISC Processor with a Rambus DRAM Controller. Solid-State Circuits Conference. Sep. 24, 1998.

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