Write through virtual cache memory, alias addressing, and cache

Details Write through virtual cache memory, alias addressing, and cache Write through virtual cache memory, alias addressing, and cache

1994-04-25

1999-08-03

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

711135, 711138, 711139, 711142, 711144, 711203, 711210, G06F 1208

Patent

active

059338440

ABSTRACT:
In a computer system comprising a CPU, a cache memory and a main memory wherein the cache memory is virtually addressed, and some of the virtual addresses are alias address to each other, a cache memory controller comprising a cache control logic, a cache tag array, a memory management unit, and an alias detection logic is provided. The cache control logic skips flushing of a cache line if the cache line is corresponding to a memory block in a non-cacheable physical memory page, thereby avoiding unnecessary flushes and allowing the CPU to update the cache memory and the main memory using an improved write through and no write allocate approach that reduces cache flushes.

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Craig R. Frink and Paul J. Roy, "A Virtual Cache-Based Workstation Architecture", (pp. 80-87), 2nd IEEE Conference on Computer Workstations (Mar. 7-10, 1988), The Compuer Society Press, Washington, D.C. *p. 82, right col., line 4-p. 83, right col., line 17*.

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