Write through function for a memory

Details Write through function for a memory Write through function for a memory

2000-02-09

2001-05-08

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S189040, C365S233100

Reexamination Certificate

active

06229754

ABSTRACT:

TECHNICAL FIELD
The invention relates to an electronic memory having multi-ports and particularly to the capability of a simultaneous read at one port while writing to the same address at a second port. Even more particularly, the invention relates to such memories with a fast operation and free of timing errors.
BACKGROUND OF THE INVENTION
High speed multi-port random access memories are used in data processing apparatus in conjunction with a general purpose or specialized central processing unit (CPU) to increase performance. One requirement of such memories is the ability to access data, either to read or write, at more than one port during a single machine cycle. For example, a high performance processor may execute an add operation of two addends by requesting the two addends simultaneously from two ports of the memory while also writing the sum (result) back into the memory on the third port all during a single machine cycle. In a pipelined machine the sum to be written back may be the result of the previous operation.
Such multi-port memories are usually required to possess a write through capability. That is, data written to a particular address on one port is required to be read out from that same address on a second port during the same cycle. Under normal operation it is therefore necessary to delay the read operation until after the write operation has placed the data into the memory at the required address. Otherwise the data read could be taken as the previous (old) contents of the address location which is not the desired data. It could also occur that the data read is some indeterminate combination of the old and current data.
Because of the great variety in memory sizes and individual speed variation, a simple delay of the read operation may not be sufficient to handle all variations in the write operation. Alternatively, setting a relatively large delay time to account for the worst possible write operation speed places a severe penalty on overall cycle time which is undesirable in high speed data processing apparatus thereby negating the purpose for which the multi-port array was selected in the first place. It is known in the art that the write through operation is generally the slowest operation of a multi-port memory and therefore tends to be the limiting factor in overall cycle time. (See col. 1 lines 53-61 of U.S. Pat. No. 4,998,221 by Correale, Jr which patent is incorporated herein by reference).
Various solutions have been developed to address this write through limitation. For example, Takeshi Eto in Japanese publication JA3-187095(A) and Loehlein in IBM Technical Disclosure Bulletin Vol. 30, No. 7, December 1987, p. 320-321 both use an address comparator to detect when two ports both desire to operate on the same address. One port is then inhibited. This approach, however, reduces overall system performance by forcing a write through operation to take two cycles while other operations may operate normally.
Clemen et al. in European publication EP0 434 852 A1 describe a multi-port SRAM with a fast single byte write capability. Incorporation of this feature also improves the speed of a write through operation by speeding up the write part of the overall cycle. However, Clemen's read part of the cycle receives data after it is written to the cell at the desires address. (See col.5, lines 15-17).
In U.S. Pat. No. 5,473,574 Clemen et al., which is incorporated herein by reference, describe a scheme for partially overlapping the write and read parts of a write through operation. (See his FIG.
6
). Clemens separates a write operation into an address decode period and a write to cell period. Likewise a read operation is separated into a read address decode period and a read from cell period. From his FIG.
6
. we see that the read decode period may overlap the write to cell period thereby shortening the overall write through cycle.
Lindner et al. in U.S. Pat. No. 5,761,147 which is incorporated herein by reference, along with Japanese publications JA1-296486, JA2-146181, JA3-29185, JA3-29187, and JA5-347096 all describe a bypass approach to the write through operation of a multi-port RAM. The bypass approach establishes an alternative data path form the write data input to the read data output. An address comparator determines when the write and read addresses coincide. In that case for a write through operation, the normal read path from the memory cell is inhibited and the alternative path is activated. With this approach there is no need to delay the read operation until after the data is written into the memory address. The data to be read is available immediately and can be read out simultaneously with the write operation, providing a much greater speedup in the write through process than provided by the partial overlap of U.S. Pat. No. 5,473,574 described above.
While conceptually appealing, the bypass process suffers from various difficulties when implemented in actual hardware with variations in size, loading, and speed noted above. In particular incorrect data errors can occur due to timing differences and glitches. Glitches are defined in the
Comprehensive Dictionary of Electrical Engineering
, CRC Press, 1999 ISBN 0-8493-3128-5, to mean “(1) an incorrect state of a signal that lasts a short time compared to the clock period of the circuit, (2) slang for a transient that causes equipment crashes, loss of data, or data errors.”
Correale, Jr. in U.S. Pat. No. 4,998,221 which is hereby incorporated by reference, describes a bypass process with circuitry to prevent glitches from being sent to the output when performing a write through operation. The circuitry of Correale is most easily explained by reference to FIG.
1
. of the present application which is a simplified block diagram based on
FIG. 6
of Correale. During a write through operation, write address decode
12
and read address decode
14
blocks will decode the same address and both access the same base cell
16
which represents just one storage cell. In general there will be a plurality of cells (not shown) corresponding to the number of bits in a word of memory. The XO
21
and XO′
22
signals are also generated by the address decoders. N/P transfer gate
18
operates by transferring the write signal on data input
13
to signal line
23
when XO and XO′ are active and presents a high impedance to signal line
23
otherwise. XO and XO′ are active during a write through operation. The write data is therefore transferred to the memory output buffer
20
directly as well as to base cell
16
. N/P transfer gate
19
operates in a similar fashion to transfer gate
18
, however the signals XO and XO′ are reversed so that the output of the base cell
15
is transferred to output buffer
20
when XO and XO′ are not active and presents a high impedance to output buffer
20
otherwise. During a write through operation the output of base cell
15
is therefore ignored and the output buffer
20
receives the correct read data directly from the write data input
13
, bypassing base cell
16
. After the write through operation is completed, XO and XO′ become inactive causing N/P transfer gate
19
to transfer whatever signal is present on base cell output
15
to output buffer
20
.
To prevent a glitch form occurring during this transition, read decode
14
is performed as during a normal read operation, to address base cell
16
, even though this data is not required because of the bypass path. Then as XO and XO′ become inactive causing N/P transfer gate
19
to transfer the base cell output signal
15
to output decoder
20
, the potential on either side of transfer gate
19
will be identical, there are no voltage spikes or glitches sent to output buffer
20
.
While in the past, memory and logic circuits were not usually combined on a single semiconductor chip due to differing technological process requirements, more recent developments now allow for much more flexibility in intermixing logic and memory circuits on a single chip. It is, now commo

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