Write strobe generation for a memory interface controller

Details Write strobe generation for a memory interface controller Write strobe generation for a memory interface controller

2011-08-02

2011-08-02

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S191000, C365S194000, C365S233100, C365S233110, C365S233140, C365S233500

Reexamination Certificate

active

07990781

ABSTRACT:
A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits.

REFERENCES:
patent: 6115322 (2000-09-01), Kanda et al.
patent: 6519188 (2003-02-01), Ryoo et al.

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