Write strategy and timing

Details Write strategy and timing Write strategy and timing

2000-06-16

2003-05-06

Bragdon, Reginald G. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S167000

Reexamination Certificate

active

06560672

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to timing of execution of activities associated with write commands in a computer system.
BACKGROUND OF THE INVENTION
A write cycle in a certain class of computer systems works with selected values associated with one or more of five consecutive bytes (a “five-byte sequence”), designated as PM (pre-mark; having a relatively high-value or “1”), PS (pre-space, having a relatively low value or “0”), MK (current mark), FS (post-space) and FM (post-mark) and illustrated in FIG.
1
. In any write cycle, several parameters must be put into place before the write cycle begins or before the parameter(s) is first used in this cycle. In a write cycle, as now implemented, the number of parameters that must be read in and stored and the number of supplementary operations that must be performed cannot be fitted into the allotted time, using a conventional approach.
Presently, the system must read and store eight parameters and perform six addition operations within five clock cycles. All activities associated with a write cycle must be completed within six clock cycles. Use of a straightforward approach to these operations will not allow completion of these operations within the allotted time.
What is needed is an approach that allows completion of these operations within the minimum allotted time (six clock cycles). Preferably, the approach should be flexible enough to permit some modification of the constraints and to permit permutations in the order of parameters used for the calculations.
SUMMARY OF THE INVENTION
These needs are met by the invention, which in one embodiment uses the following. Three of the eight parameters are pre-read in a clock cycle before the six-clock-cycle sequence begins, using a relatively inactive cycle in the preceding sequence, from two selected registers and from a selected SRAM location and stored. The five remaining parameters are read from five SRAM locations and stored during the first five clock cycles of a six-clock-cycle sequence, with the sixth clock cycle in this sequence being used to perform the six addition operations.


REFERENCES:
patent: 6249901 (2001-06-01), Yuan et al.

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