Write recovery time control circuit in semiconductor memory and

Details Write recovery time control circuit in semiconductor memory and Write recovery time control circuit in semiconductor memory and

1998-12-09

2000-08-22

Nelms, David

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

365194, 36523006, G11C 700

Patent

active

061082457

ABSTRACT:
The write recovery time control circuit includes a power control signal generating circuit, a decoder circuit and a write disabling signal generating circuit. The power control signal generating circuit generates a power control signal based on a cell block address signal, at least one bit of a predecoded address signal, and a write disabling signal. The decoder circuit generates word line selection signals based on the predecoded address signal and the power control signal. The write disabling signal generating circuit generates the write disabling signal such that changes in said power control signal are delayed by a predetermined period of time.

REFERENCES:
patent: 5091889 (1992-02-01), Hamano et al.
patent: 5357479 (1994-10-01), Matsui
patent: 5495449 (1996-02-01), Park

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