Write pulse signal generating circuit for a semiconductor memory

Details Write pulse signal generating circuit for a semiconductor memory Write pulse signal generating circuit for a semiconductor memory

1989-01-09

1991-06-25

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365174, 365177, 307446, 307267, G11C 700, H03K 1902, H03K 3017, H03K 504

Patent

active

050273230

ABSTRACT:
A semiconductor integrated circuit device includes a pulse width expander circuit for expanding the pulse width of a pulse signal of the ECL (emitter coupled logic) level that has a very narrow pulse width, a level conversion circuit for converting the output signal of the ECL level of the pulse width expander circuit into a CMOS (complementary metal oxide semiconductor) level, and an internal circuit that is so connected as to receive the output signal of the level conversion circuit. In other words, the pulse signal having a narrow pulse width is expanded to have a pulse width which is sufficient for the level conversion circuit prior to performing the level conversion operation. Therefore, the level of the pulse signals having narrow pulse widths is stably converted.

REFERENCES:
patent: 3641519 (1972-02-01), Ashley
patent: 4337523 (1982-06-01), Hotta et al.
patent: 4435793 (1984-05-01), Ochii
patent: 4697109 (1987-09-01), Honma et al.
patent: 4713796 (1987-12-01), Ogiue et al.
patent: 4802126 (1989-01-01), Takayama
patent: 4829479 (1989-05-01), Mitsumoto et al.
Ogiue et al., "13-ns, 500-mW, 64-kbit ECL RAM Using HI-BICMOS Technology", IEEE Journal of Solid-State Circuits vol. SC-21, No. 5, Oct. 1986, pp. 681-685.
Kitsukawa et al., "An Experimental 1-Mbit BiCMOS RAM," IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 657-661.

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