Write pass through circuit

Details Write pass through circuit Write pass through circuit

1996-01-19

1997-08-12

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

365221, 36523003, 36523009, G11C 800

Patent

active

056572921

ABSTRACT:
A write global bus driver is provided within the data input buffer. The write global bus driver has the same circuit configuration as the read global bus driver so that it drives the output buffer with the very same type of signal and in the same way as the read global bus driver drives the output buffer. The write global bus driver is coupled to the global data bus for placing written data on the global data bus that is normally used only for read data. During each write cycle, the data is written simultaneously to the memory array and to the output buffer. The output buffer is a two-stage, pipelined output buffer. When data is stored in the first stage of the output buffer, whether write data or read data, it is maintained in the first stage on the same clock cycle that it is presented. On the subsequent clock cycle, the data from the first stage is transferred to the second stage and is provided as the output of the output buffer. In the event a read cycle immediately follows a write cycle, the write data is provided as the output from the output buffer as a result of the first read cycle being performed. During the second read cycle, the data read during the first read cycle is provided as the output.

REFERENCES:
patent: 5251181 (1993-10-01), Toda
patent: 5258952 (1993-11-01), Coker et al.
patent: 5267197 (1993-11-01), McClure
patent: 5267210 (1993-11-01), McClure et al.
patent: 5293623 (1994-03-01), Froniewski et al.
patent: 5300828 (1994-04-01), McClure
patent: 5305268 (1994-04-01), McClure
patent: 5311467 (1994-05-01), Lysinger et al.
patent: 5341341 (1994-08-01), Fukuzo
patent: 5521878 (1996-05-01), Ohtani et al.

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