Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2003-03-20
2004-03-30
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S181000, C365S182000
Reexamination Certificate
active
06714436
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The subject invention relates generally to the design and operation of semiconductor devices and, more particularly, to the design and operation of a single-transistor capacitorless (1T/0C) random access memory (RAM) cell, wherein data is written to the cell through utilization of a band-to-band tunneling (BTBT) mechanism in a manner that modulates the threshold voltage of the cell.
2. Related Art
A number of RAM designs based on CMOS technology are prominent in the art. (See, for example, Neil H.E. Weste and Kamran Eshraghian,
Principles of CMOS VLSI Design:
Addison-Wesley, 1994, pp. 563-585). Perhaps the most commonly used CMOS RAM configuration is predicated on a six-transistor cross-coupled inverter. However, more recently, single-transistor MOS RAMs have appeared that store data on a capacitor connected to a pass transistor. In general, sense amplifiers operate to detect a small voltage differential that arises when a selected cell is switched onto a bit line.
A variety of approaches have been adopted to implement the data-storage capacitor in a single-transistor MOS RAM. For example, the capacitor may be implemented simply as a second transistor. Alternatively, an appreciable reduction in semiconductor real estate that is occupied by the RAM cell may be realized by the adoption of a trench capacitor structure or a stacked capacitor structure. Nevertheless, there remains a persistent requirement to reduce the area occupied by a RAM cell beyond that which appears feasible through a transistor/capacitor configuration. The 1T/0C memory cell is a response to this demand, and numerous ramifications of the 1T/0C design have been proposed. To wit: John E. Leiss, et al., “dRAM Using the Taper-Isolation Dynamic Cell,”
IEEE Transactions on Electron Devices,
Vol. Ed. 29, No. 4, April 1982 (pp. 707-714), describes a MOS transistor with a buried channel structure. Data storage is effected by respectively charging and discharging a surface inversion layer through a parasitic transistor that is formed at a taper portion of an element isolation film. However, the cell structure described by Leiss, et al. is relatively complicated and its operation depends on the characteristics of the parasitic transistor, which are likely to prove insufficiently controllable and repeatable in production quantities.
In another approach, data is represented as a threshold voltage of a MOS transistor, wherein the threshold voltage is determined by the well potential of individual transistors in a memory array. See Japanese Patent Laid-Open Publication No. H3-171768. The resulting structure is relatively straightforward, but requires that both the drain and the source be coupled to separate conductors so that the applied bias voltages may be independently controlled. Moreover, the cell size tends to be substantial, and programming on a bit-by-bit basis is unavailable because electrical and physical isolation must be maintained between cells.
Marnix R. Tack, et al., “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures,”
IEEE Transactions on Electron Devices,
Vol. 37, May, 1990 (pp. 1373-1382), describes a memory cell in which a MOS transistor is formed on an SOI substrate. Data storage is realized here by applying a large negative voltage from the SOI substrate side of the cell. As a result, holes are caused to accumulate in an oxide film. Alternative logic states are represented by the respective emission or injection of holes from or to the oxide layer. This approach is compromised by the necessity to apply the negative bias from the SOI substrate, again precluding the capability of programming on a bit-by-bit basis.
Hsing-jen Wann, et al., “A Capacitorless DRAM Cell on SOI Substrate,”
IEDM
93 (pp. 635-638), similarly proposes a memory cell in the form of a MOS transistor on an SOI substrate. In this device, a conduction layer of a conductivity type opposite to the conductivity type of the transistor is formed on the drain diffusion area of the MOS transistor. In this manner, read and write operations are performed by respective integrated nMOS (read) and pMOS (write) transistors. The substrate of the nMOS transistor is an effective floating node so that data is represented by the potential of the nMOS substrate. To its detriment, this cell configuration relies on a relatively exotic device design and demands a similarly involved interconnect scheme, including a word line, a write bit line, a read bit line, and a purge line.
United States Patent Pub. No. US200210051378, “Semiconductor Memory Device and Method of Manufacturing the Same,” describes a (1T/0C) memory cell in which each cell exhibits a floating body region that is isolated from the floating body region of every other cell in the array. Specifically, the memory cell incorporates an SOI structure in which an nMOS transistor is formed in a p-type body region, over a silicon dioxide insulating film. N-type drain and diffusion regions are formed to the depth of the insulating film so that the body region is isolated at its bottom surface by the insulating layer, on its sides by the respective drain and source regions, and at its upper surface by the gate structure. Data is represented in the cell by modulating the threshold voltage of the MOS transistor. In particular, a logic level ONE is asserted through the accumulation of majority carriers (holes) in the p-type body region. The accumulation of holes is manifested as a decrease in the device threshold voltage. Production of holes is precipitated by the impact ionization mechanism. A second logic level (e.g., ZERO) results as holes are emitted from the body region upon the application of a forward bias to the PN junction on the drain side of the memory cell. Although the above-described memory cell is commendable in its simplicity of structure, it suffers from a notable inefficiency in operation. That is, the generation of majority carriers through impact ionization requires a drain current that may be orders of magnitude greater than the hole current it supports. Clearly, the wasteful dissipation of power is contraindicated in many applications. In addition, impact ionization is known to be detrimental to the MOS transistor current and transconductance characteristics.
Accordingly, existing approaches to the design and implementation of a RAM cell structure have been unavailing in satisfying multifarious requirements that include compatibility with small device geometries, simplicity of device structure and fabrication, amenability to low-power operation, and reliability.
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Burnett James D.
Hoefler Alexander
Lebentritt Michael S.
Motorola Inc.
Nguyen Hien
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