Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-06-17
2001-03-13
Myers, Paul R. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S027000
Reexamination Certificate
active
06202116
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to communication of data in an electronic system and more particularly to a bus providing general communication capabilities.
2. Description of the Related Art
In electronic systems, busses transfer data between two parts of the system and typically between two or more integrated circuits. For example, in a computer system, one or more busses provide the path to transfer data (which may include control information) between a processor and an external device such as a printer, video monitor, keyboard, hard or floppy disk, etc. In the past, busses, such as those used on printed circuit boards to transfer data between integrated circuits, have operated at frequencies in which the transfer time needed to pass data between circuits coupled to the bus was comparatively insignificant. Many such busses are bi-directional allowing a circuit on the bus to perform both read and write operations on the bus. During a write operation, the circuit writing data sends data to another circuit on the bus. During a read operation, the reading device indicates that a read operation is taking place and specifies the address of the data it wants to read. The reading device provides this information but then allows the other circuit on the bus to provide the read data. That generally requires that the bus be “turned around” so that the bus can be driven from the circuit providing the data rather than from the circuit receiving the data. That requires that the circuit that is receiving read data on the bus turn off its drivers to ensure the bus is at a high impedance state. That allows the circuit providing the read data to drive the bus at suitable voltage levels.
However, advances in semiconductor technology have resulted in much higher frequencies of bus operation. As a result, the time required to turn around the direction of a bus is a much higher percentage of the total bus bandwidth than in the past. As the frequency of bus operations gets higher in the future, that percentage will continue to grow.
For example, a bus may be operating at 1 gigahertz (GHz.), or one nanosecond per transfer of data. To achieve this operating speed, present high speed bus approaches utilize a point-to-point bus, which connects no more than two integrated circuits. A clock must typically be sent from each side to the other side (clock forwarding) to make sure that the data is synchronized to a clock as it is received. However, it may take up to 5 nanoseconds for data to be transmitted from one side of the bus to the other, depending of course on a number of factors including, e.g., the length of the bus. If, as is typical of busses, there is an arbiter for the bus in one location, a bus request by one integrated circuit to the arbiter in another integrated circuit would typically require about 5 nanoseconds for transmission, another 5 nanoseconds to change clock domains, another 5 nanoseconds to transmit the grant, and still another 5 nanoseconds to change clock domains again. So, in total, up to 20 nanoseconds have been consumed in order to acquire the bus for a bus cycle that may need to be only 5 or 10 nanoseconds long.
Thus, it would be desirable to provide a high speed bus in which the impact of turning the bus around is minimized and the utilization of the bus is maximized.
SUMMARY OF THE INVENTION
Accordingly, the present invention splits the data bus in half and dedicates half of the bus to transfer data from one side of the bus to the other and the other half of the bus to transfer data in the opposite direction. Bus cycles that originate from one side of the link only go one direction (from the originator to the other side). In order to avoid inefficiency because half of the bus may become unused if a long bus cycle is going in one direction while nothing is being transferred in the opposite direction, one side can take over the whole data bus during a transmission over its half of the data bus and transfer data over both sides of the bus.
Accordingly, in one embodiment of the invention a method of communicating on a bus is provided. The bus, which couples a first and second bus interface circuit, includes a plurality of data lines divided into a first group and a second group. The method includes transferring first data over the first group data lines from the first to the second bus interface circuit during a first time period on the bus. Second data is transferred over the bus from the second to the first bus interface circuit over the second group of data lines during the first time period. Third data is transferred over the bus from the first to the second bus interface circuit over the first and second group of data lines during a second time period, the second time period being different from the first time period.
In another embodiment of the invention a bus interface circuit for interfacing to a bus, includes a first transmit controller coupled to transmit first data in half bus mode to a first group of data lines of the bus during a first time period. The bus interface circuit further includes a first receive controller that receives second data in half bus mode from a second group of data lines of the bus during the first time period. The bus interface circuit, responsive to a granted request, transmits third data in whole bus mode to the first and second group of data lines during a second time period, the second time period being different from the first time period.
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Advanced Micro Devices , Inc.
Myers Paul R.
Zagorin O'Brien & Graham LLP
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