Static information storage and retrieval – Read only systems
Reexamination Certificate
2002-06-21
2004-10-12
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read only systems
C365S177000
Reexamination Certificate
active
06804136
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits and, more particularly, to write once read only memory employing charge trapping in insulators.
BACKGROUND OF THE INVENTION
Many electronic products need various amounts of memory to store information, e.g. data. One common type of high speed, low cost memory includes dynamic random access memory (DRAM) comprised of individual DRAM cells arranged in arrays. DRAM cells include an access transistor, e.g a metal oxide semiconducting field effect transistor (MOSFET), coupled to a capacitor cell. With successive generations of DRAM chips, an emphasis continues to be placed on increasing array density and maximizing chip real estate while minimizing the cost of manufacture. It is further desirable to increase array density with little or no modification of the DRAM optimized process flow.
A requirement exists for memory devices which need only be programmed once, as for instance to function as an electronic film in a camera. If the memory arrays have a very high density then they can store a large number of very high resolution images in a digital camera. If the memory is inexpensive then it can for instance replace the light sensitive films which are used to store images in conventional cameras.
Thus, there is a need for improved DRAM technology compatible write once read only memory. It is desirable that such write once read only memory be fabricated on a DRAM chip with little or no modification of the DRAM process flow. It is further desirable that such write once read only memory operate with lower programming voltages than that used by conventional DRAM cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.
REFERENCES
L. Forbes, W. P. Noble and E. H. Cloud, entitled “MOSFET Technology for Programmable Address Decode and Correction,” U.S. Pat. No. 6,521,950;
L. Forbes, E. Sun, R. Adlers and J. Moll, “Field Induced Re-Emission of Electronics Trapped in SiO
2
,” IEEE Trans. Electron Device, vol. ED-26, No. 11, pp. 1816-1818 (Nov. 1979);
S. S. B. Or, N. Hwang, and L. Forbes, “Tunneling and Thermal Emission from a Distribution of Deep Traps in SiO
2
,” IEEE Trans. on Electron Devices, vol. 40, No. 6, pp. 1100-1103 (Jun. 1993);
S. A. Abbas and R. C. Dockerty, “N-Channel IGFET Design Limitations Due to Hot Electron Trapping,” IEEE Int. Electron Devices Mtg., Washington D.C., Dec. 1975, pp. 35-38;
B. Eitan et al., “Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM Device,” IEEE Electron Device Lett., vol. 22, No. 11, pp. 556-558, (Nov. 2001);
B. Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett., vol. 21, No. 11, pp.
543-545
, (Nov. 2000);
S. Sze, Physics of Semiconductor Devices, Wiley, N.Y., 1981, pp.
504-506
);
L. Forbes and J. Geusic, “Memory Using Insulator Traps,” U.S. Pat. No. 6,140,181.
SUMMARY OF THE INVENTION
The above mentioned problems for creating DRAM technology compatible write once read only memory cells as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. This disclosure teaches structures and methods using MOSFET devices as write once read only memory in a DRAM integrated circuit. The structures and methods use the existing process sequence for MOSFET's in DRAM technology.
In particular, an illustrative embodiment of the present invention includes a write once read only memory cell. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET). The MOSFET has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A plug is coupled to the first source/drain region. The plug couples the first source/drain region to an array plate. A transmission line is coupled to the second source/drain region. The MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the first source/drain region. Accordingly, the channel region has a first voltage threshold region (Vt
1
) and a second voltage threshold region (Vt
2
) such that the programmed MOSFET operates at reduced drain source current.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
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Micro)n Technology, Inc.
Phung Anh
Schwegman Lundberg Woessner & Kluth P.A.
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