Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-08-12
2001-07-24
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S222000, C711S103000, C711S106000
Reexamination Certificate
active
06266282
ABSTRACT:
This application claims priority from Korean patent application No. 98-32937 filed Aug. 13, 1998 in the name of Samsung Electronics Co., Ltd., which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to computer systems, and more particularly, to a method for writing to a synchronous flash memory device in a computer system having a synchronous random access memory device sharing a system bus with the synchronous flash memory device.
2. Description of the Related Art
Electrically programmable read-only memories (EPROMs) and electrically erasable and programmable read-only memories (EEPROMs), are used as nonvolatile memory in microcomputers (and microcontrollers). With both types of programmable read-only memories, a complete write operation requires an erase operation and a program operation. With an EPROM, data is erased by projecting ultraviolet light at a particular portion, and then new data is programmed therein. The EPROM must be separated from the circuit board during erasure because the ultraviolet light affects other elements on the board. With the EEPROM, however, data is erased by applying electrical signals to the EEPROM, and then new data is programmed therein.
Since a select transistor is provided in each cell of an EEPROM, the size an EEPROM cell is larger than that of an EPROM cell, so it is difficult to achieve high integration densities with EEPROM cells. To solve this problem, flash memory devices have been developed in which each of the EEPROM cells is configured by means of only one transistor. When a flash memory device is used as a nonvolatile memory in a microcomputer, it must receive and transmit information to and from the exterior of the chip (for example, from a microprocessor, a synchronous random access memory device, etc.) at high speeds. Therefore, flash memory devices, which operate in synchronization with a clock signal, have been developed. Such a synchronous flash memory device is disclosed in U.S. Pat. No. 5,586,081, entitled “SYNCHRONOUS ADDRESS LATCHING FOR MEMORY ARRAYS”, which is herein incorporated by reference.
A synchronous flash memory device can be implemented so as to share the same system bus with the synchronous random access memory device under the control of a microprocessor. However, the operation of, or data stored in, the synchronous random access memory device can be affected by a program/erase operation of the synchronous flash memory device.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for writing to a synchronous flash memory device which shares a system bus with a synchronous random access memory device.
To prevent the program and erase operations of a synchronous flash memory device from affecting the operation of, or data stored in, a synchronous random access memory device which shares the system bus, the present invention sets the synchronous random access memory device to refresh mode before a program or erase operation is performed in the synchronous flash memory device. After the program or erase operation is completed, the synchronous random access memory device is placed back in normal mode. If data is to be transferred from the synchronous random access memory device to the synchronous flash memory device, the data is read from the synchronous random access memory device and stored temporarily in the synchronous flash memory device before the synchronous random access memory device is set in refresh mode.
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patent: 5893135 (1999-04-01), Hasbun et al.
Hwang Seong-Don
Kim Myong-Jae
Mai Son
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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