Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-02-21
2003-12-09
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S194000
Reexamination Certificate
active
06661716
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to data transfer circuits for semiconductor memory devices, and more particularly to write circuits and methods for content addressable memories (CAMs).
BACKGROUND OF THE INVENTION
Due to the increased prevalence of information networks, including the Internet, content addressable memories (CAMs) continue to proliferate. CAMs, sometimes referred to as “associative memories” can provide rapid matching functions that are often needed in routers and network switches to process network packets. As just one example, a router can use a matching function to match the destination of an incoming packet with a “forwarding” table. The forwarding table can provide “next hop” information that can allow the incoming packet to be transmitted to its final destination, or to another node on the way to its final destination. Of course, CAMs can also be used for applications other than network hardware.
An overview of a typical conventional CAM architecture will now be described, with particular emphasis on how data is written into the memory.
A CAM may generally be partitioned into smaller arrays (or “sub-arrays”), each sharing a common data bus. Referring to
FIG. 5
, an example of a CAM that is partitioned into eight smaller sub-arrays is shown, and is designated by the general reference character
500
. The CAM
500
is shown to include periphery circuits
502
that may generate signals that route to eight CAM sub-arrays,
504
-
0
to
504
-
7
.
CAM sub-arrays (
504
-
0
to
504
-
7
) may each include a local write circuit
506
that writes data into CAM cells
510
by way of bitline signals
514
.
A data bus
518
may include a relatively large number of data signal line (e.g., greater than about 70, more particularly greater than 100, even more particularly about 144). Data signals may be placed on data signal lines
518
by periphery circuits
502
, thereby transferring data to each CAM sub-array
504
-
0
to
504
-
7
. A write enable signal
512
may also be generated by periphery circuits
502
and connect to each CAM sub-array
504
-
0
to
504
-
7
. A write enable signal
512
may be used to initiate a write operation.
A write operation in a typical conventional CAM
500
may be performed by asserting data signals
518
to desired data states, and then activating a write enable signal
512
to a predetermined state (e.g., high). Data on data signals
518
may then be written into CAM sub-arrays
504
-
0
to
504
-
7
. It is understood that this is a simplified description of an actual conventional write implementation. In some cases, the write operation may also be controlled according to a clock signal, for example.
CAMs are used in many applications such as network routers and switches where reliable, high-speed operation is very desirable. Thus, it is important that the write operation described above be performed reliably and as quickly as possible. An important factor in achieving this goal is in the timing of a write enable signal
512
relative to data signals
518
. If a write operation is initiated before data on data signal lines
518
is valid, incorrect data may be written into the CAM sub-arrays.
Many factors can affect the time it may take for data on data signals
518
to propagate to CAM sub-arrays
504
-
0
to
504
-
7
. For example, there may be many CAM write circuits
506
spread across each CAM sub-array. Thus, in some cases data may propagate for a shorter distance, while in other cases data may propagate for a longer distance to reach a CAM sub-array (
504
-
0
to
504
-
7
). Also, there may be a large number of data signals routed together across the CAM array. The routing location for some data signals can therefore be physically located further away from the CAM write circuits
506
than others, which means there may be a longer propagation delay associated with such longer routed data signals.
Another factor that can affect signal speed is capacitive coupling between adjacent signal lines. It is well known that there can be a parasitic capacitance between signals routed on an integrated circuit. Thus, if a data signal is transitioning in one direction (e.g. from low to high) while data signals on either side are transitioning in the opposite direction (high to low in this case), then the capacitive coupling between the lines can cause the transition of the signal to slow down. It follows that a worst case coupling can occur if signals on both sides of the data signal in question are transitioning in the opposite direction to the data of the data signal itself.
The timing of the write enable signal
512
can therefore be affected by one or all of the factors described above.
Typically, a conventional circuit that generates a write enable signal
512
can have a means of delaying the signal to account for the above described factors. It may not be possible to precisely predict the effect of the above factors, however, since they may change as a result of wafer processing variations or due to different operating conditions of the device, as but two examples. In practice, extra margin or “guardband” may be added to such a timing delay of a write enable signal
512
to account for these uncertainties. By adding such guardband delay, write operations may be made more reliable.
A drawback to introducing delay (including guardband noted above) into a write enable signal can be additional time that may be needed for a write operation. Write operations may need additional time as time that could have been used to actually write data to the CAM sub-arrays is now used to provide margin to ensure that correct data is written.
It would therefore be desirable to provide a way to time the write enable signal relative to data signals that may require less guardband than conventional approaches.
SUMMARY OF THE INVENTION
According to disclosed embodiments, a content addressable memory (CAM) may include data signals connected to multiple CAM core circuits and a write control signal that is routed along side the data signals. CAM core circuits may include write circuits that transfers data on data signals lines to CAM cells. Write circuits may be enabled in response to a write control signal.
According to one aspect of the embodiments, a write control signal line may be routed to be at least as long as the longest of the data signal lines.
According to another aspect of the embodiments, a write control signal may be surrounded by signals of the opposite polarity.
According to another aspect of the embodiments, the data signals may include both true and complement signals. There may be more than 100 pairs of true and complement data signals.
According to another aspect of the embodiments, true and complement data signals may be used to indicate at least three different functions; a write “1”, a write “0”, and a mask operation.
According to another aspect of the embodiments, repeater circuits may be used to regenerate data signals and write control signals.
According to another aspect of the embodiments, a clocked register circuit and a delay circuit may be used to generate a write control signal.
REFERENCES:
patent: 5319589 (1994-06-01), Yamagata et al.
patent: 5452243 (1995-09-01), Ansel et al.
Cypress Semiconductor Corporation
Le Thong
Sako Bradley T.
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