Write data masking for higher speed drams

Details Write data masking for higher speed drams Write data masking for higher speed drams

2002-08-19

2003-11-04

Nguyen, Vanthu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S120000, C365S230060

Reexamination Certificate

active

06643194

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to data masking circuits and data masking methods for semiconductor memory devices.
2. Description of the Related Art
Electronic equipment and electronic-based systems require some form of high-speed memory devices for storing and retrieving information. While the type of such memory devices vary, semiconductor memory devices are most commonly used in memory applications requiring implementation in relatively small areas. Within this class of semiconductor memory devices, random access memory (RAM) is one of the common types. A RAM incorporates an array of individual memory cells. A user may execute both read and write operations on the memory cells of a RAM. A typical example of a RAM is a dynamic random access memory (DRAM), as is well known in the art.
To allow a DRAM to operate at high speed, “synchronous” DRAMS, also referred to a SDRAMs, have been developed. A synchronous DRAM can receive a system clock that is synchronous with the processing speed of the overall system. The internal circuitry of the SDRAM can be operated in such a manner as to accomplish read/write operations in synchronism with the system clock.
SDRAMs include Single Data Rate (SDR) SDRAMs and Double Data Rate (DDR) SDRAMs. In a SDR SDRAM, data can be input and output at either only the rising edge or only the falling edge of a clock signal. In a DDR SDRAM, data can be input and output at both the rising and falling edges of the clock signal. Therefore, the DDR SDRAM can have a data bandwidth which is twice the clock frequency.
It is also known to use a data input/output mask signal applied externally to the memory device to mask output data from the memory device during a read operation and to mask input data to the memory device during a write operation. For example, situations occur when it is desired to send a data stream to a memory device, but it is also desired that some of the data stored in the memory device remain the same. A data mask can be used to block some of the data in the data stream from reaching the individual memory cells that should remain undisturbed.
FIG. 1
illustrates in block diagram form a portion of a conventional memory device
20
in which data write masking is used. The memory depicted illustrates a single bank (BANK
0
) of a 64 Meg SDRAM. BANK
0
memory array
22
includes memory cells arranged in rows and columns for storing data. Command decoder
24
, included in control logic
26
, receives control signals from a command bus CMD to place control logic
26
in a particular operation sequence. Control logic
26
controls the various circuitry of SDRAM
20
based on decoded commands such as reads or writes from or to memory bank
22
. A specific address for which a read or write command is to occur is provided to address register
28
, which provides the address to row-address multiplexer
30
and column-address counter
32
. Row address multiplexer
30
provides a row address to row decoder
34
, which decodes the row address and activates one of the lines corresponding to the row address in BANK
0
22
for a read or write transfer operation. Column address counter
32
provides a column address to column decoder
36
, which activates the I/O gating
38
of the column corresponding to the column address. Data being written to the memory
20
is input on data lines (DQ) via the input/output datapath logic circuit
40
, driven by write drivers
42
and passed to the I/O gates
38
for writing to the array
22
. During a read operation, data from the array
22
is passed through the I/O gates
38
to read latch
44
to datapath logic circuit
40
and output on the data lines (DQ).
Conventional data masking during a write operation is accomplished by sending a mask control signal (DM) through the datapath logic circuit
40
to the write drivers
42
at the same time the data stream is being routed through the write drivers
42
. This mask control signal causes the write driver
42
to go “tri-state” or high impedance, blocking the data stream's path to the I/O gates
38
. As illustrated in
FIG. 1
, each write driver
42
drives 8 bits of data (D
0
-D
7
, D
8
-D
15
, D
16
-D
23
, D
24
-D
32
, respectively) for a total of 32 bits or 4 bytes. Four data mask signals are provided (DM
0
, DM
1
, DM
2
, DM
3
), one for each group of 8 bits or byte.
FIGS. 2A and 2B
are timing diagrams of various signals generated in the memory device
20
during a write operation with data masking. In order to save space, in
FIGS. 2A
,
2
B,
4
A, and
4
B, the data lines (DQ
0
-DQ
31
) are not individually shown. Instead, each group of data lines corresponding to each byte of data are shown. Thus, XB
0
represents the group of data lines corresponding to the first byte of data (DQ
0
-DQ
7
), XB
1
represents the data lines corresponding to the second byte of data (DQ
8
-DQ
15
), XB
2
represents the data lines corresponding to the third byte of data (DQ
16
-DQ
23
), and XB
3
represents the data lines corresponding to the fourth byte of data (DQ
24
-DQ
31
). Additionally, several signals are prefixed with “X”, “Y”, or “Z”. These prefixes indicate different points in time, wherein X designates the time at which a memory device is presented with the write command, Y designates the time after the write command and the associated memory address has been decoded, but before the time when the data is written to the memory arrays of the memory device, while Z indicates the time when the memory arrays are written. Thus, the timing diagrams of
FIGS. 2A
,
2
B,
4
A, and
4
B, permit the reader to follow the relationship between the data signals and data mask signals relative to other signals in the memory device as the data travels through the memory device.
In
FIG. 2A
, the illustrated memory device
20
is a 32-bit wide (x32) memory undergoing 16-byte write of data bytes B
0
-B
15
. Since the memory device is 32-bit or 4-bytes wide, the memory device accepts 4-bytes per clock cycle for writing on data byte lines XB
0
-XB
3
. In order for the memory device to support per-byte data masking, the memory device must support one data mask line (XDM
0
-XDM
3
) per data byte line (XB
0
-XB
3
). At a first clock cycle of the clock CLK, the WRITE command is present on the command bus CMD. Not illustrated, but also present is the address associated with the first data byte B
0
. Present shortly after the write command are the data (B
0
-B
15
) to be written as well as an associated data mask on data mask lines XDM
0
-XDM
1
.
Referring now to
FIG. 2B
, it can be seen that data on signal lines YB
0
-YB
3
and the data mask on data mask signal lines YDM
0
-YDM
3
have been delayed by an identical amount due to the need for the command decoder
24
to decode the write command and the column decoder
36
and row address decoder
34
to decode the address. At this point data is present on the data lines YB
0
-YB
3
can be driven by the write drivers
42
to the I/O gates
38
if the write driver enable lines WD
0
-WD
3
are high. As shown, data which is to be written, for example data B
0
-B
5
, B
8
-B
10
, and B
12
-B
15
, are accompanied by a high write driver enable signal to permit the data to be driven to the I/O gates
38
while the column select signal ZCS
0
-ZCS
3
associated with those bytes are also driven high to activate the proper column in the memory array, thereby permitting the data to be written to the array
22
. On the other hand, when data needs to be masked from writing, for example data B
6
, B
7
, and B
11
, the data mask signal YDM
0
-YDM
3
is high, causing the write driver signal WD
0
-WD
3
to go low, thereby preventing masked data from being driven to the I/O gates
38
and written to the array
22
.
As illustrated in
FIG. 2B
, the column select lines ZCS
8
-ZCS
3
are fired each time regardless of whether data is to be masked nor not. Between each successive firing of the column selects, there is a time period x at which the column select is

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