Write data error checking in a PCI Bus system

Details Write data error checking in a PCI Bus system Write data error checking in a PCI Bus system

2000-03-09

2003-03-04

Baderman, Scott (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S043000

Reexamination Certificate

active

06530043

ABSTRACT:

The incorporated '610 application describes an example of a complex PCI bus system for providing a connection path between a secondary PCI bus, to which are attached a plurality of agents, such as channel adapters, and at least one primary bus to which is attached a peripheral device server. The incorporated '610application additionally defines many of the terms employed herein, and such definitions are also available from publications provided by the PCI Special Interest Group, and will not be repeated here. Complex PCI bus systems, such as that of the incorporated '610 application, employ arbitration between commands from the attached channel adapters on the PCI bus system to manage the usage of the bus system in an efficient manner.
Computer data storage systems may employ PCI bus systems to provide fast data storage from hosts, such as network servers, via channel adapters and the PCI bus system, to attached storage servers having storage devices, cache storage, or non-volatile cache storage. It is advantageous to provide data storage that operates at relatively fast speeds which approach or match the speeds of the host processors, or that release the host processors, such that the host processors are not slowed. The incorporated '610 application additionally defines many of the terms employed herein, and such definitions are also available from publications provided by the PCI Special Interest Group, and will not be repeated here.
A typical requirement of any data transfer system, such as a PCI bus system, is to provide verification of write data transferred by the system. Thus, typically, write data is encoded in accordance with an error checking algorithm, such as a longitudinal redundancy check algorithm (LRC), or a cyclic redundancy check algorithm (CRC), and the resultant check character appended to the write data. The data is then checked at the other side of the PCI bus system by the same algorithm, including the check character, and, if the data is error free, the remainder of the redundancy calculation is typically an all zero output. Also typically, data transfers, including write data transfers, are conducted in a variable number of fixed sized blocks of data, such as blocks of 512 bytes of data, and the check character is appended at the end of the data. A block may alternatively comprise a single multibyte word. The error check may be conducted at the receiving device only, but will not identify the source of the error.
Thus, redundancy calculation logic has been provided as a part of many PCI bus systems in order to better isolate and identify the source of the error. Two problems result. First, the host channel adapter that originated the write data transfer will send a read command to the PCI bus system upon completion of the write data transfer and read the contents of a register which stores the calculated check value. The read must have a return path which is maintained while the read operation passes through the bus system and then the check value is returned along the path, making a read operation slow and inefficient. Second, the host channel is stalled and must remain locked to the bus, and the bus elements are held until the read command results are correctly received.
As the result, the redundancy check read operation is both slow to complete and prevents other activities at the bus.
An alternative approach is to provide hardware that sends an interrupt to the host adapter if there is a problem. The difficulty is that the hardware must know that the write data transfer from the host channel adapter is complete, and requires extensive and costly logic to identify that the transfer is completed and to respond.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method and system for promptly determining the redundancy check value for write data completely transferred across a PCI bus.
In a PCI bus system having at least one PCI bus, at least one PCI data source, and at least one PCI data destination, a method and system are provided for checking errors in write data transferred from the PCI data source, across the PCI bus, to the PCI bus system, for the PCI data destination, the data comprising a plurality of blocks. The error checking system comprises a storage memory, and redundancy calculation logic coupled to the PCI bus and to the storage memory. The redundancy calculation logic receives the write data across the PCI bus, calculating a check value for each block of the data transferred across the PCI bus, and updating each calculated check value with any previously calculated check value at a storage location of the storage memory. Data path logic is coupled to the PCI bus and to the storage memory, and responds to a subsequently sent redundancy write command sent, e.g., from the PCI data source. The write command is highly efficient in PCI bus systems, so as to allow the PCI bus system to provide a prompt response. The subsequently sent redundancy write command has an unique identifier and provides an address which relates to the storage location of the check value, and is sent subsequent to completion of the transfer of the write data across the PCI bus.
The data path logic responds to the write command unique identifier, detecting the updated calculated check value at the storage location of the storage memory. Error check logic coupled to the data path logic determines whether the detected updated calculated check value indicates an error, and upon the detected updated calculated check value indicating an error, signaling the error.
In accordance with one embodiment of the present invention, the subsequently sent redundancy write command unique identifier comprises at least one bit of a PCI address of the write command. The bit is outside the range of addresses employed for decoding the address of the target.
For a fuller understanding of the present invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings.


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