Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2002-08-30
2004-10-19
Phung, Anh (Department: 2824)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S189011, C365S189040
Reexamination Certificate
active
06807087
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to electronic devices, especially magnetic random access memories, and more specifically to magnetic random access memory arrays compensated for write current shunting.
2. Description of the Related Art
Magnetic random access memory (MRAM) typically is made up of memory cells that store information based on a direction of magnetization of a ferromagnetic region. MRAM cells can hold stored information for long periods of time, and are thus nonvolatile.
MRAM memory generally takes the form of an array of intersecting, electrically-conductive column and row lines formed on a substrate. An MRAM memory cell is located at each intersection of the array.
Various types of MRAM memory cells are known in the prior art. U.S. Pat. No. 5,640,343, issued Jun. 17, 1997 to Gallagher et al., discloses an MRAM device that utilizes an array of Magnetic Tunnel Junction (MTJ) memory cells. Each MTJ MRAM memory cell includes a magnetic tunnel junction. As shown in
FIG. 7
, a magnetic tunnel junction
70
includes three functional layers: a free ferromagnetic layer
72
, a tunnel barrier
74
, and a fixed or pinned ferromagnetic layer
76
. The magnetization direction of pinned layer
76
is fixed by exchange coupling with an antiferromagnctic material. The magnetization direction of the free ferromagnetic layer
72
, in the absence of an applied field, is oriented along either a positive or a negative axis, as indicated by the double-headed arrow.
Conductance of the MTJ memory cell is determined by the alignment of the magnetization in the fixed and free ferromagnetic layers. Accordingly, binary information can be stored in each memory cell based on the relative alignment of the magnetization direction in each layer. When the alignment is parallel (both magnetizations oriented in the same direction) the MTJ has a lower magnetoresistance, representing a logic 0, for example. When the alignment is antiparallel (the magnetizations oriented in opposite directions), the resistance of the MTJ is higher, representing a logic 1. The magnetoresistance is the result of spin-polarized tunneling of conduction electrons between the ferromagnetic layers. Measuring the magnetoresistance indicates the alignment, and thus the logical state, of the cell.
Changing the orientation of the magnetization of the free ferromagnetic layer changes the logic state of the cell. The magnetization of the free layer will rotate in the presence of an applied magnetic field. The magnetic field is applied by way of an electric current flowing in the conductive word and bit lines. A current in both lines generates a magnetic field of sufficient strength to change the orientation state of the memory cell. The current of at least one of the lines has to be reversible to write the two different magnetic states of the cell.
SUMMARY OF THE INVENTION
The present invention overcomes the deficiencies of the prior art by compensating for write current shunting in an MRAM array. Write current shunting is defined as the undesired leakage current that flows through an MRAM cell during a write operation, due to the finite resistance of the cell and the difference in the potentials of write conductors on opposite sides of the cell. According to a preferred embodiment, MRAM cells are arranged along a write line such that the cells progressively increase in physical size, from the high potential side to the low potential side. Write current requirements decrease with increasing cell size. Consequently, write current shunting is compensated by making cells larger at the end of the write line farthest from the high potential voltage input.
According to one aspect of the invention, the array is designed so that the cell width increases monotonically from high to low potential side of the write line. According to another aspect of the invention, compensating for current shunt by distributing cell size in the array allows more bits to be provided on the same write line, thereby reducing the number of transistors in the array and increasing bit density.
REFERENCES:
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patent: 5640343 (1997-06-01), Gallagher et al.
patent: 5734605 (1998-03-01), Zhu et al.
patent: 5793697 (1998-08-01), Scheuerlein
patent: 6215707 (2001-04-01), Moyer
patent: 6351409 (2002-02-01), Rizzo et al.
patent: 6385079 (2002-05-01), Tran
patent: 6466475 (2002-10-01), Nickel
patent: 6490217 (2002-12-01), DeBrosse et al.
patent: 6538921 (2003-03-01), Daughton et al.
patent: 6621730 (2003-09-01), Lage
Dickstein , Shapiro, Morin & Oshinsky, LLP
Luu Pho M.
Phung Anh
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