Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2001-12-03
2003-08-19
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S212000, C365S242000
Reexamination Certificate
active
06608790
ABSTRACT:
TECHNICAL FIELD
The technical field is cross point memory devices. More specifically, the technical field is memory devices having write circuitries that vary write currents in order to compensate for coercivity changes that occur as a result of temperature variations in a memory array.
BACKGROUND
Magnetic Random Access Memory (MRAM) is a proposed type of non-volatile memory. Accessing data from MRAM devices is much faster than accessing data from conventional long term storage devices such as hard drives.
FIG. 1
illustrates a conventional MRAM memory array
10
having resistive memory cells
12
located at cross points of row conductors
14
and column conductors
16
. Each memory cell
12
is capable of storing the binary states of “1” and “0.”
FIG. 2
illustrates a conventional MRAM memory cell
12
. The memory cell
12
includes a pinned layer
24
and a free layer
18
. The pinned layer
24
has a magnetization that has a fixed orientation, illustrated by the arrow
26
. The magnetization of the free layer
18
, illustrated by the bi-directional arrow
28
, can be oriented in either of two directions along an “easy axis” of the free layer
18
. If the magnetizations of the free layer
18
and the pinned layer
24
are in the same direction, the orientation of the memory cell
12
is “parallel.” If the magnetizations are in opposite directions, the orientation is “anti-parallel.” The two orientations correspond to the binary states of “1” and “0, ” respectively. The free layer
18
and the pinned layer
24
are separated by an insulating tunnel barrier layer
20
. The insulating tunnel barrier layer
20
allows quantum mechanical tunneling to occur between the free layer
18
and the pinned layer
24
. The tunneling is electron spin dependent, making the resistance of the memory cell
12
a function of the relative orientations of the magnetizations of the free layer
18
and the pinned layer
24
.
Each memory cell
12
in the memory array
10
can have its binary state changed by a write operation. Write currents Ix and Iy supplied to the row conductor
14
and the column conductor
16
crossing at a selected memory cell
12
switch the magnetization of the free layer
18
between parallel and anti-parallel with the pinned layer
24
. The current Iy passing through the column conductor
16
results in the magnetic field Hx, and the current Ix passing through the row conductor
14
results in the magnetic field Hy. The fields Hx and Hy combine to switch the magnetic orientation of the memory cell
12
from parallel to anti-parallel. A current −Iy can be applied with the current Ix to switch the memory cell
12
back to parallel.
In order to switch the state of the memory cell
12
from parallel to anti-parallel, and vice versa, the combined field created by +/−Hx and Hy exceeds a critical switching field Hc of the memory cell
12
. The current magnitudes for Ix and Iy must be carefully selected because if Hx and Hy are too small, they will not switch the orientation of the selected memory cell
12
. If Hx and Hy are too large, memory cells
12
on the row conductor
14
or the column conductor
16
of the selected memory cell
12
may be switched by the action of either Hx or Hy acting alone. These unselected memory cells
12
are referred to as “half-selected” memory cells.
A problem arises in conventional MRAM arrays because operating an array and ambient temperature changes may cause the temperature of the array to vary, which causes the coercivity of the memory cells to change. A change in coercivity of the memory cells changes the critical switching field Hc, which in turn changes the fields Hx and Hy required to switch the state of the cells. This condition increases the likelihood that an entire row or column of half-selected memory cells will be programmed due to the action of Ix or Iy alone, or the likelihood that the write currents Ix and Iy will be insufficient to switch a selected memory cell.
A need therefore exists for a memory device capable of accurately compensating for coercivity changes in a memory array. A need also exists for a memory device capable of compensating for coercivity changes without undue complexity.
SUMMARY
According to a first aspect, a memory device comprises a memory array having a substrate, an array of memory cells disposed over the substrate, a plurality of row conductors coupled to the memory cells, and a plurality of column conductors coupled to the memory cells. The memory device also includes one or more current sources that generate variable write currents in response to temperature changes in the memory array. The variable write currents are generated to accommodate changes in coercivity of the memory cells as the temperature of the array changes. A current source includes a temperature sensor that may provide a continuous, immediate output to ensure accurate adjustment of write currents generated by the current source.
According to the first aspect, the current source can automatically compensate for temperature variations in the array according to the output from the temperature sensor. There is no need to halt operation of the memory device to calibrate the current source. Also according to the first aspect, the current source provides an accurate adjustment to the write current because the temperature used by the temperature sensor to generate the output may be taken contemporaneously with generation of the write current.
Also according to the first aspect, the adjustment of the write currents may be effected by an analog input from the temperature sensors. Digital processing is not required in order to adjust the write currents, reducing the complexity of the memory device.
According to a second aspect, a method of generating a write current in a memory device includes the steps of applying a first voltage to a temperature sensor, enabling a write current to flow to one of a plurality of conductors, receiving an output from the temperature sensor at the current source, and adjusting the write current according to the output from the temperature sensor.
According to the second aspect, the write current generated can be adjusted without halting device operation. The write current is appropriate for switching the memory cells in the memory array because the temperature used by the temperature sensor to generate the output may be taken contemporaneously with generation of the write current. In addition, the write current can be generated using analog operations, which reduces the complexity of the write process.
REFERENCES:
patent: 5793697 (1998-08-01), Scheuerlein
patent: 6128239 (2000-10-01), Perner
patent: 6181103 (2001-01-01), Chen
patent: 6369712 (2002-04-01), Letkomiller et al.
patent: 6385082 (2002-05-01), Abraham et al.
patent: 6476716 (2002-11-01), Ledlow
patent: 2002/0105748 (2002-08-01), Lamberts
Bhattacharyya Manoj K.
Tran Lung T.
Hewlett--Packard Development Company, L.P.
Ho Hoai
Pham Ly Duy
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