Write control for a memory using a delay locked loop

Details Write control for a memory using a delay locked loop Write control for a memory using a delay locked loop

1994-03-08

1995-08-08

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Signals

365233, 327158, 327250, 327277, G11C 710

Patent

active

054405149

ABSTRACT:
A memory (20) includes a write control delay locked loop (52) for controlling a write cycle of the memory (20). The delay locked loop (52) includes an arbiter circuit (264), a voltage controlled delay (VCD) circuit (260), and a VCD control circuit (265). The arbiter circuit (264) compares a clock signal to a delayed clock signal from the VCD circuit (260). In response, the arbiter circuit (264) provides a retard signal to the VCD control circuit (265). The VCD control circuit (265) receives the retard signal and adjusts a propagation delay of the delayed clock signal to compensate for changes in the clock frequency, as well as to compensate for process, temperature, and power supply variations.

REFERENCES:
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Terry I. Chappell et al., "A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM", Feb., 1991 IEEE International Solid-State Circuits Conference, pp. 50,51 & 288.

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