Write command verification across a PCI bus system

Details Write command verification across a PCI bus system Write command verification across a PCI bus system

2000-02-15

2003-03-18

Heckler, Thomas M. (Department: 2185)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Reexamination Certificate

active

06535937

ABSTRACT:

DOCUMENTS INCORPORATED BY REFERENCE
Commonly assigned U.S. patent application Ser. No. 09/275,610, filed Mar. 24, 1999, is incorporated for its showing of a PCI bus bridge system for processing requests from multiple attached agents.
FIELD OF THE INVENTION
This invention relates to the verification of write commands in a PCI bus system, and, more particularly, to such verification in a complex PCI bus system having at least two PCI busses.
BACKGROUND OF THE INVENTION
The Peripheral Component Interconnect (PCI) bus system is a high-performance expansion bus architecture which offers a low latency path employing PCI bridges through which a host processor may directly access PCI devices. In a multiple host environment, a PCI bus system may include such functions as data buffering and PCI central functions such as arbitration over usage of the bus system.
The incorporated '610 application describes an example of a complex PCI bus system for providing a connection path between a secondary PCI bus, to which are attached a plurality of hosts, and at least one primary PCI bus, to which is attached a peripheral device server. The incorporated '610 application additionally defines many of the terms employed herein, and such definitions are also available from publications provided by the PCI Special Interest Group, and will not be repeated here.
Computer system data storage systems may employ PCI bus systems to provide fast data storage from hosts, such as network servers, via channel adapters and the PCI bus system, to attached data storage servers having storage devices, cache storage, or non-volatile cache storage. It is advantageous to provide data storage that operates at relatively fast speeds which approach or match the speeds of the host processors, or release the host processors, such that the host processors are not slowed.
The data to be stored is typically customer data which will be retrieved at a subsequent time. It is of the utmost importance to the customer that the customer data not be lost or compromised. Thus, in addition to fast data storage, there must be some assurance that customer data that has been transmitted across the PCI bus system, has not been lost. Hence, most channel adapters for the hosts require an acknowledgment that their data transfer write operations have completed successfully.
In PCI bus systems, the channel adapters perform PCI write commands to transfer data to their destinations. Channel adapters generally poll (a PCI read command) a hardware indicator that signals “End of Transfer”, or issue a PCI read command to a location as far down the data path as possible in an attempt to acquire an acknowledgment that the data transfer had completed successfully.
Complex PCI bus systems, such as that of the incorporated '610 application, employ arbitration between commands from the attached channel adapters on the PCI bus system to manage the usage of the bus system in an efficient manner. One element of PCI architecture is that PCI read commands are not allowed to supersede or pass PCI write commands. Therefore, once the PCI read command has returned the data which has been read back to its originator, it is safe to assume that the prior PCI write command(s) were completed. Thus, upon receiving the read data, the channel adapter has the desired acknowledgment.
Read operations are slow and inefficient because, after initiation of a read, a substantial wait is required while the data is accessed and loaded for passage back through the bus system. Therefore, the architecture blocks the requester from the PCI bus until after the data is loaded, so as to allow other uses of the bus by other requesters. An element of arbitration is that the adapter sending a read command must receive the response within a predetermined time, or will have to give up the interface as the arbitrator cycles to the next agent having work. As the result, the originator continues to request the read results which are ultimately provided to a buffer to match the request. Therefore, PCI read commands are extremely slow operations to complete, especially in complex PCI bus systems with multiple hosts and with multiple PCI bridges between the channel adapters and the storage system. During the time required to complete the read, the host adapter that originated the original writes which are being verified must pause and wait for the read command to be completed before receiving an acknowledgment that the write operation completed successfully, effectively locking up the host adapter.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method and system for asynchronously and promptly verifying the passage of at least one write command and data sent at an initiating PCI bus through the PCI bus system to a location substantially at the end of the PCI bus system, allowing the originator to do additional work in the interim.
In a PCI bus system having at least one PCI bus, a method and system are provided for verifying the passage of one or more write commands and their accompanying data sent at the PCI bus through the PCI bus system from an originating location coupled to the PCI bus to a location towards an end of said PCI bus system. The PCI bus system is implemented to transmit write commands on a FIFO basis. The passage verifying system comprises an addressable location substantially at the end of the PCI bus system with respect to the PCI bus. In one embodiment, the addressable location comprises storage for receiving and storing data accompanying a write command. A write command is sent subsequent to the one or more write commands at the initiating PCI bus, the subsequently sent write command addressed to a predetermined special end location address identifying the addressable location, the subsequently sent command accompanied by data comprising a predetermined special return address of the originating location. The FIFO PCI bus system causes the one or more write commands to precede the subsequently sent write command. Logic coupled to the addressable storage senses the subsequently received write command, and responds thereto, sending a return echo write command to the predetermined special return address. Thus, the return echo write command verifies the passage of the one or more write commands and data through the PCI bus system from the originating location to the location substantially at the end of the PCI bus system.
In one embodiment, the logic employs the predetermined special end location address as a key to identify the subsequently sent write command and to send the return echo write command.
In a further embodiment, the logic additionally sends the predetermined special return address as data accompanying the return echo write command. Thus, the predetermined special return address confirms to the originator the passage of the write commands and data through the PCI bus system.
As the subsequently sent write command is processed asynchronously, the originating agent is freed to conduct additional work.
For a fuller understanding of the present invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings.


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patent: 5838932 (1998-11-01), Alzien
patent: 5870567 (1999-02-01), Hausauer et al.
patent: 5911051 (1999-06-01), Carson et al.
patent: 5918028 (1999-06-01), Silverthorn et al.
patent: 5928346 (1999-07-01), Johnson et al.

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