Write clock and data window tuning based on rank select

Details Write clock and data window tuning based on rank select Write clock and data window tuning based on rank select

2002-01-22

2004-10-12

Padmanabhan, Mano (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S202000, C711S206000, C711S208000, C711S167000, C714S006130, C714S731000

Reexamination Certificate

active

06804764

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory sub-systems, and more specifically to a technique for tuning signals based on the physical location of the signal destination.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In today's high speed computer systems, requests are initiated to the memory sub-system in rapid succession. Historically, memory devices in the memory sub-system have been controlled asynchronously by the processor. In asynchronous systems, the processor strobes the requested address using row and column address select pins on the memory device. The addresses associated with the requests are held for a required minimum length of time. During the hold time, the memory device accesses the address location and after some delay, called the “access time,” the memory device writes new data from the processor into its memory or provides data from the address location to its outputs for the processor to read. During this time, the processor waits for the memory device to perform internal functions such as precharging the lines, decoding the addresses, sensing the data, and routing the data through the output buffers. This creates a “wait state” during which the high speed processor is waiting for the memory device to respond. Disadvantageously, this wait state slows the processing speed of the entire system.
An alternate strategy is to provide synchronous control in the system. Synchronous control refers to memory devices which latch information from the processor in and out of the memory devices under the control of a system clock. One particular type of synchronous control is called “source synchronous.” Source synchronous systems deliver data along with a clock or strobe signal on the same transmission line. The processor may receive a cycle time indicating how many clock cycles it takes for the memory device in the memory sub-system to complete its task so that the processor can simultaneously perform other tasks while the memory device is processing its request. Advantageously, synchronous systems reduce or eliminate propagating multiple timing strobes through the system since the system clock may be the only timing edge that is provided to the memory sub-system. Synchronous timing simplifies the inputs of the memory device from an external perspective as well, since all signals, addresses, and data can be latched simultaneously rather than requiring the processor to monitor various timings such as setup and hold times. The output data is also simplified since the data will be in the output buffer latch on the appropriate cycle and the processor needs only to clock it out. Further, complex timing diagrams, which may be necessary to operate asynchronous memory systems, are not required in synchronous systems.
Synchronous systems, however, do offer additional design challenges. One such challenge is maintaining optimal alignment of a data or command signal with respect to the clock signal. Because data is latched on a rising or falling clock edge, it is generally desirable to align the clock edge with the strongest point in the data signal, usually the center of the periodic peek or the “eye” of the data. In systems incorporating multiple memory slots arranged along a bus, data integrity may be different at different slot locations. Each of the slots may be configured to hold a memory module comprising a plurality of memory devices. In a high speed computer memory sub-system with multiple slots or ranks of memory, each rank has a different physical location relative to the other ranks and the memory controller which may be tasked with providing access to each of the various memory slots. Data integrity is difficult to maintain and varies depending on the physical location of the slot as well as the loading at various points in the memory sub-system. Because a request signal may look different at various locations along the bus, it is difficult to align the clock signal such that it is optimized for requests going to the various slots along the memory bus. What is optimal for a memory module at a first location may not be optimal for a memory module at a second physical location along the bus since the data eye may be shifted, skewed, or degraded.
The present invention may address one or more of the concerns set forth above.


REFERENCES:
patent: 5758056 (1998-05-01), Barr
patent: 6092165 (2000-07-01), Bolyn
patent: 6292903 (2001-09-01), Coteus et al.
patent: 6330683 (2001-12-01), Jeddeloh
patent: 6442722 (2002-08-01), Nadeau-Dostie et al.
patent: 6556489 (2003-04-01), Gomm et al.

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