Write circuit for a semiconductor memory device

Details Write circuit for a semiconductor memory device Write circuit for a semiconductor memory device

1999-02-02

2002-03-05

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S189110, C365S189180, C365S226000

Reexamination Certificate

active

06353559

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to a write circuit for a semiconductor memory device, and more particularly, to the stabilization of the write potential supplied to a memory cell transistor of a semiconductor memory device.
An Electrically Erasable and Programmable ROM (EEPROM) is equipped with a memory cell transistor with a double gate structure consisting of a floating gate and a control gate. In data writing of the memory cell transistor, some hot electrons that move from a drain region to a source region are injected into the floating gate. In data reading, the differences between the operating characteristics of a memory cell when electric charge is injected into the floating gate and the operating characteristics of the memory cell when the electric charge is not injected into the floating gate are detected. In other words, changes in the threshold of the memory cell are detected.
FIG. 1
is a schematic block diagram of a conventional semiconductor memory device. In this diagram, the memory device has four rows and one column. However, it is well known in the art that memory cell transistors can be arranged over plural rows and columns.
A memory cell transistor
1
has an electrically independent floating gate and a control gate having a portion that covers the floating gate. The memory cell transistor I turns on and off in accordance with a potential applied to the control gate and changes its own threshold in accordance with the amount of electric charge accumulated in the floating gate.
The control gate of the memory cell transistor
1
of each row is connected to a word line
2
provided on each row, respectively. The drain of the memory cell transistor
1
in one column is connected to a sense amp (not illustrated) via a common bit line
3
. The source of each memory cell transistor
1
is connected to a source line
4
arranged between the respective memory cell transistors
1
.
A row decoder
5
receives row address information and generates row selection signals LS
1
to LS
4
that selectively activate any one of the four word lines
2
in accordance with a selection clock signal &phgr;L. The selection signals LS
1
to LS
4
are supplied to the memory cell transistors
1
through the word lines
2
and the control gate of the selected memory cell transistor
1
is turned on. If the memory cell transistors
1
are arranged over plural columns, a column decoder that selects one column is used in accordance with column address information. Thus, the one memory cell transistor
1
selected in accordance with the low address information (and the column address information) is connected to the sense amp.
A read controller
6
is connected to the bit line
3
and supplies a read potential Vd
1
to the bit line
3
in accordance with a read clock signal &phgr;R. A write controller
7
is connected to the source line
4
and supplies a write potential Vd
2
to the source line
4
in accordance with a write clock signal &phgr;W. The read controller
6
and the write controller
7
supply a ground potential Vs, except during the periods in which the read potential Vd
1
and the write potential Vd
2
are supplied.
In data writing, the ground potential Vs (for example, 0 V) is applied to the drain of the memory cell transistor
1
through the bit line
3
, and the write potential Vd
2
(for example, 14 V) is applied to the source of the memory cell transistor
1
through the source line
4
. Accordingly, in the selected memory cell transistor
1
, write current flows from the source region to the drain region and an electric charge is injected into the floating gate.
In data reading, the read potential Vd
1
(for example, 5 V) is applied to the drain of the memory cell transistor
1
through the bit line
3
, and the ground potential Vs (for example, 0 V) is applied to the source of the memory cell transistor
1
through the source line
4
. Accordingly, in the selected memory cell transistor
1
, read current flows from the drain region to the source region. At this time, the memory cell transistor
1
has a threshold that corresponds to the amount of electric charge (i.e., write information) accumulated in the floating gate. Consequently, the potential of the bit line
3
that corresponds to the threshold is read using the sense amp.
In data writing, as the amount of electric charge injected into the floating gate of the memory cell transistor
1
increases, the threshold change of the memory cell transistor
1
increases. As a result, in data reading, the write data is more easily determined. However, increasing the amount of electric charge prolongs the write time. Accordingly, it is not desirable to inject more electric charge into the floating gate than is necessary. In general, the minimum amount of electric charge is injected into the floating gate such that a sufficient change of threshold to determine the write data can be obtained.
Because the write potential Vd
2
is higher than the normal power supply potential, the high potential Vhv generated using a booster (not illustrated) is supplied to the write controller
7
, and the write potential Vd
2
is supplied to the source line
4
by the write controller
7
. Accordingly, the current flowing in the memory cell transistor
1
is determined according to the current supply capacity of the booster. Further, the amount of electric charge injected into the floating gate is controlled by the amount of current flowing in the memory cell transistor
1
and the current flow time. If the booster operates unstably due to factors such as fluctuations of the power supply potential, the current flowing in the memory cell transistor
1
fluctuates. Consequently, the amount of electric charge injected into the floating gate fluctuates.
It is an object of the present invention to provide a write circuit for a semiconductor memory device that stably writes data into a memory cell transistor.
SUMMARY OF THE INVENTION
Briefly stated, the present invention provides a write circuit for supplying a write potential that is higher than a power supply potential to memory cells of a semiconductor memory device. The device includes a reference potential generator that generates a reference potential having a substantially constant potential difference from one of a power supply potential and a ground potential. A voltage-controlled oscillator (VCO) connected to the reference potential generator receives the reference potential and generating an oscillation clock signal having an oscillation clock frequency in proportion to the reference potential. A booster connected to the VCO that generates a write potential by piling up the oscillation clock signal onto the power supply potential in a multistage manner. A write controller is connected to the booster and supplies the write potential to the memory cells in accordance with a write clock.
The present invention provides a method of generating a write potential that is higher than a power supply potential to memory cells of a semiconductor memory device. First, a reference potential is generated that has a substantially constant potential difference from one of a power supply potential and a ground potential. Then, an oscillation clock signal having an oscillation clock frequency is generated in proportion to the reference potential. A write potential is generated by piling up the oscillation clock signal onto the power supply potential in a multistage manner. Then, the write potential is supplied to the memory cells in accordance with a write clock.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


REFERENCES:
patent: 5446418 (1995-08-01), Hara et al.
patent: 5615146 (1997-03-01), Gotou
patent: 5661686 (1997-08-01), Gotou
patent: 5889719 (1999-03-01), Yoo et al.
patent: 5969565 (1999-10-01), Naganawa
patent: 5991221 (1999-11-01), Ishikawa et al.
patent: 0 710 959 (1996-05-01), None

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