Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2001-11-29
2002-07-02
Verbrugge, Kevin (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
Reexamination Certificate
active
06415365
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing apparatus for buffering addresses identifying locations in a memory, and data values to be written to those memory locations. The term ‘data value’ is used herein to refer to both instructions and to items or blocks of data, such as data words.
2. Description of the Prior Art
A typical data processing apparatus includes a processor core (or CPU) arranged to execute a sequence of instructions that are applied to data supplied to the processor core. Generally, a memory may be provided for storing the instructions and data (collectively referred to herein as “data values”) required by the processor core. Further, it is often the case that one or more caches are provided for storing data values required by the processor core, so as to reduce the number of accesses required to the memory.
Whilst the use of a cache improves the processing speed of the processor core, there is still the requirement for the processor core to read data values from, and write data values to, the memory, and these processes are relatively slow, thereby adversely affecting the processing speed of the processor core.
To alleviate the impact on processing speed resulting from writing data values to a memory, it is known to provide a write buffer that is typically arranged to decouple a cached CPU from the memory, so as to allow the processor bus to complete a write operation to the intermediate write buffer, and for that write buffer to then autonomously perform the write to the memory bus. By this approach, the CPU does not need to wait for the write process to complete before proceeding to execute the next instruction. Further, the write buffer depth can be increased beyond a single register to enable a plurality of CPU data writes to be buffered, for example by using a First-In-First-Out (FIFO) buffer to maintain write transaction ordering.
In general terms, a write buffer presents a “slave” interface to a “master” at its input side, and presents an “initiator bus” interface to the memory bus on its output side. The slave interface generally requires address (a), control (c) and write data (d) signals. The control signal will typically include control information such as operand size, protection and access flags. The master interface, for example the interface between the CPU and the processor bus, similarly must source the same address, control and write data information, and may additionally perform funnelling to narrower or wider data bus width.
In a simple prior art write buffer, the slave interface of the write buffer will have a width of “a+c+d” bits (for address, control and data bus widths). In such an arrangement, the write buffer storage requirements are:
a+c+d bits wide x number of write buffer slots.
Generally, when developing data processing apparatus, such as integrated circuits, there is a desire to keep the circuit as small as possible. The space that an integrated circuit occupies is at a premium. The smaller an integrated circuit is, the less expensive it will be to manufacture and the higher the manufacturing yield. For this reason, it is clear that the number of write buffer slots provided within the write buffer cannot be increased at will, as the overall size of the integrated circuit must be kept as small as possible.
Whenever the write buffer fills to capacity, the processor stalls on a subsequent write operation until a free slot in the write buffer becomes available. The maximum write buffer depth is application dependent, and is a trade off between chip area, sustainable burst write bandwidth, and the “latency” of the memory, or secondary, bus where a read transaction is blocked until the write buffer has been emptied.
For cached processors and higher bandwidth systems, much of the write traffic is in the form of “bursts” (i.e. cache line replacements or stack context saves), where a base address and a fixed or variable number of data words are transferred. However, there will still typically be some non-burst (eg. 8-bit and 16-bit) accesses (eg. character or “short” data).
In such arrangements, the area required by the write buffer may be reduced by separating the address/control paths from the data path so as to provide two logically separate write buffers, one for the address and control signals, and one for the data signals. Since there will generally be less addresses than data values in burst mode operation, then the number of address slots provided in the write buffer can be significantly less than the data slots provided in the write buffer. However, this saving in area to provide fewer address slots is typically traded for more data slots, such that the overall area of the write buffer is optimized for typical usage.
Hence, for such burst mode write buffers, the write buffer storage is:
a+c bits wide x number of address slots
d bits wide x number of data slots
In such an arrangement, an address incrementer is typically required to re-synthesize the burst addresses as the contents of the write buffer are output to memory, and more complex control logic is required to interlock the address and data write buffer reconstruction.
Whilst such an arrangement is clearly advantageous for burst mode write traffic, if there are any non-burst stores (i.e. byte structure access), then the number of address slots becomes a limiting factor, since in this non-burst mode, there will be one address for each data word.
Given that many data processing apparatus typically employ both burst mode and non-burst mode stores to memory, it would be desirable to provide the data processing apparatus with a write buffer that operates efficiently for both burst mode write traffic and non-burst mode write traffic, without having to increase the size of the write buffer with respect to the size of known prior art write buffers.
SUMMARY OF THE INVENTION
Viewed from a first aspect, the present invention provides a data processing apparatus comprising: a processor core for generating addresses identifying locations in a memory and data values for storing in the memory; a write buffer for storing the addresses and data values output by the processor core, and for subsequently outputting said addresses and data values to cause the data values to be stored in said memory; the write buffer comprising a plurality of rows, each row being arranged to store an address or data value, and each row having associated therewith a flag field settable to indicate whether that row contains an address or a data value.
In accordance with the present invention, each row of the write buffer is able to store either an address or a data value, an additional flag field is associated with each row, and the flag field is settable to indicate whether that row contains an address or a data value. Hence, in burst-mode, a particular row will be used to store the base address, with the flag field for that row being set accordingly to indicate that an address is contained within that row, and then subsequently the data values forming the burst traffic will be stored in other rows of the write buffer, with the flag fields of those rows being set to indicate that data values are contained within those rows. This approach makes very efficient use of the available write buffer area when buffering burst mode write traffic.
However, it is clear that the arrangement of the present invention also supports non-burst write traffic, where the rows of the write buffer will alternately store addresses and data values, with the flag fields for each row being set accordingly.
It has been found that a write buffer in accordance with the present invention can be arranged to occupy a relatively small area, whilst providing a good compromise between a write buffer optimized for non-burst mode traffic, and a write buffer optimized for burst mode traffic.
In preferred embodiments, each row comprises ‘n’ bits and the flag field comprises one or more of said ‘n’ bits. Preferably, said flag field comprises a single bit, since th
Arm Limited
Nixon & Vanderhye P.C.
Verbrugge Kevin
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