Write bias generator for column multiplexed static random access

Details Write bias generator for column multiplexed static random access Write bias generator for column multiplexed static random access

1997-12-31

1999-05-25

Nelms, David

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365154, 365156, G11C 700, G11C 1100

Patent

active

059075104

ABSTRACT:
This invention is useful in column multiplexed memories, particularly static random access memories (SRAM) used in application specific integrated circuits (ASIC) . These column multiplexed memories include memory cells disposed in rows and columns. For writes all the bitlines are connected to a bias generator. The bias generator uses first P-channel field effect transistor and a first N-channel field effect transistor connected in series with their junction connected to the bitline. The bias generator is driven by a bias enable pulse that is active for a short time before the write time. Normally these field effect transistors are biased OFF by a second P-channel field effect transistor and a second N-channel field effect transistor. Another pair of N-channel field effect transistors connect the bases of the first P-channel field effect transistor and the first N-channel field effect transistor together to the bitline when the bias enable pulse is active. The first P-channel field effect transistor and the first N-channel field effect transistor are constructed with a ratio of channel widths equal to the ratio of the P-channel and N-channel field effect transistors in an input inverter of the latch of the memory cell. The second P-channel field effect transistor has a channel width much greater than the channel width of the second N-channel field effect transistor.

REFERENCES:
patent: 4764899 (1988-08-01), Lewallen et al.
patent: 5276647 (1994-01-01), Matsui et al.

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