Write-back cache with ECC protection

Details Write-back cache with ECC protection Write-back cache with ECC protection

1990-10-01

1993-08-03

Beausoliel, Robert W.

Excavating

371 402, G06F 1110

Patent

active

052336166

ABSTRACT:
This invention relates to a write-back cache which is protected with parity and error correction coding ("ECC"). The parity and ECC codes are generated by a memory interface when data is transferred by main memory to the central processing unit ("CPU") associated with the cache. Thus, all data originating in main memory will be parity and ECC encoded when it passes through the memory interface, and the data, and its related parity information and ECC codes will be stored in the cache. On the other hand, data which is taken from the cache and modified by the CPU during its processing operations is also transferred to the memory interface for ECC encoding. Thus, all data modified by the CPU is also protected, and the modified data, and its related parity information and ECC codes are also stored in the cache. The memory interface also contains ECC checking and correcting circuitry which can correct erroneous data, on the basis of its ECC code, if that data has been corrupted while stored in the cache, or during transmission on a bus. Therefore, if data in the cache is corrupted, it can be corrected when it is returned to main memory via the memory interface. Accordingly, the invention makes a write-back cache compatible with full ECC protection, even though, at times, the cache may contain the only correct, current copy of given data in the system.

REFERENCES:
patent: 4084236 (1978-04-01), Chelberg
patent: 4791642 (1988-12-01), Taylor
patent: 4794521 (1988-12-01), Ziegler
patent: 4862462 (1989-08-01), Zulian
patent: 4920539 (1990-04-01), Albonesi
patent: 4995041 (1991-02-01), Hetherington
patent: 5058116 (1991-10-01), Chao

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