Write-assisted SRAM bit cell

Details Write-assisted SRAM bit cell Write-assisted SRAM bit cell

2003-04-02

2004-10-12

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S203000

Reexamination Certificate

active

06804143

ABSTRACT:

TECHNICAL FIELD
This invention facilitates efficient writing of data into a static random access memory (SRAM) bit cell, particularly if a logic 0 value stored in the bit cell is to be overwritten by a logic 1 value.
BACKGROUND
FIGS. 1 and 2
schematically depict a typical prior art single binary digit (i.e. 1-bit) SRAM bit cell incorporating cross-coupled inverters
10
,
12
. Inverter
10
is formed by PMOS “pull-up” transistor
14
and NMOS “pull-down” transistor
16
. PMOS transistor
14
's source is connected to a logic “high” voltage reference (V
DD
), PMOS transistor
14
's drain is connected in series with NMOS transistor
16
's drain, NMOS transistor
16
's source is connected to a logic “low” voltage reference (ground), and PMOS transistor
14
's gate is connected to NMOS transistor
16
's gate. Inverter
12
is formed by PMOS pull-up transistor
18
and NMOS pull-down transistor
20
. PMOS transistor
18
's source is connected to V
DD
, PMOS transistor
18
's drain is connected in series with NMOS transistor
20
's drain, NMOS transistor
20
's source is connected to ground, and PMOS transistor
18
's gate is connected to NMOS transistor
20
's gate. Inverters
10
,
12
are cross-coupled by connecting the gates of PMOS transistor
14
and NMOS transistor
16
to the drains of PMOS transistor
18
and NMOS transistor
20
to define a first storage node S
1
; and, by connecting the gates of PMOS transistor
18
and NMOS transistor
20
to the drains of PMOS transistor
14
and NMOS transistor
16
to define a second storage node S
2
. The source-to-drain path of NMOS pass transistor
22
is connected between first storage node S
1
and first bit line BIT, and the gate of NMOS transistor
22
is connected to word line WL. The source-to-drain path of NMOS pass transistor
24
is connected between second storage node S
2
and second bit line {overscore (BIT)}, and the gate of NMOS transistor
24
is connected to word line WL.
Pass transistors
22
,
24
are selectively turned on or off via word line WL to read or write data from the bit cell via bit lines BIT, {overscore (BIT)}. The cross-coupled structure of inverters
10
,
12
ensures that logically opposite voltages are maintained at first and second storage nodes S
1
, S
2
respectively. To read the single bit value stored in the bit cell, a logic high voltage signal is applied to word line WL, turning pass transistors
22
,
24
on, thereby coupling nodes S
1
, S
2
to bit lines BIT, {overscore (BIT)} respectively and allowing the bit cell to apply a differential voltage signal to bit lines BIT, {overscore (BIT)} which is in turn amplified by sense amplifiers (not shown). The sizes of transistors
14
through
24
are selected to accommodate writing of a single bit value into the bit cell by either pulling bit line BIT and node S
1
low to drive node S
2
high; or, pulling bit line {overscore (BIT)} and node S
2
low to drive node S
1
high when pass transistors
22
,
24
are turned on. The cross coupled inverters latch the new data. Large numbers of such bit cells are combined to form memory arrays.
FIGS. 3 and 4
schematically depict another prior art SRAM bit cell incorporating cross-coupled inverters, as described in U.S. Pat. No. 5,754,468. The
FIG. 3
bit cell is similar to the
FIG. 1
bit cell, except:
NMOS pass transistor
24
is replaced with PMOS pass transistor
26
;
word line WL is replaced with a dedicated write enable line and a complementary dedicated read enable line;
NMOS transistor
22
and PMOS transistor
26
are decoupled from one another—NMOS transistor
22
's gate is instead connected to the write enable line and PMOS transistor
26
's gate is connected to the complementary read enable line; and,
bit lines BIT, {overscore (BIT)} are replaced with single-ended (true or complement) write and read buses respectively.
In the
FIGS. 3 and 4
embodiment, data is written into the bit cell by applying a logic high voltage signal to the write enable line, thereby turning NMOS transistor
22
on and coupling node S
1
to the write bus. Data is read from the bit cell by applying a logic low voltage signal to the complementary read enable line, thereby turning PMOS transistor
26
on and coupling node S
2
to the read bus, which is preferably pre-charged to a logic low state, since PMOS transistor
26
pulls up better than it pulls down.
The writing of a logic 0 value from the write bus through NMOS transistor
22
into the
FIGS. 3 and 4
bit cell is a relatively “strong” event, in the sense that NMOS transistor
22
inherently pulls down to ground, so if a logic 1 value is already stored at node S
1
that value is easily overwritten by the logic 0 value. However, the writing of a logic 1 value through NMOS transistor
22
into the
FIGS. 3 and 4
bit cell is a relatively “weak” event, in the sense that if a logic 0 value is already stored at node S
1
, NMOS transistor
22
tends to shut off before the stored logic 0 is overwritten by the logic 1 value. Consequently, the operation of writing of a logic 1 value into the
FIGS. 3 and 4
bit cell may fail or require an unacceptably long period of time. One way to compensate for this is to preferentially increase the sizes of the transistors in inverters
10
,
12
so that a “weak” logic 1 value driven onto inverter
10
's node S
2
cross-couples through inverter
12
to complete the writing event at node S
1
. While this technique can be made to work, the drawback is that larger transistors consume additional integrated circuit silicon area and power. In a memory array consisting of many cells, the increased silicon area can be considerable.
This invention addresses the foregoing drawbacks of the
FIGS. 3 and 4
bit cell, addresses further drawbacks inherent to single-ended bit line cells, and provides novel techniques for splitting rows of cells into 2 or more separate groups.
SUMMARY OF INVENTION
The invention allows efficient writing of data into an SRAM bit cell. In cells configured with separate read and write buses, whenever a write operation is performed, the read bus is forcibly held in a pre-charge state (pulled to ground) during the entire write operation. In cells configured with a common (single-ended) read/write bus, the pass transistor on the side of the cell opposite to the read/write bus is turned on during the entire write operation, reducing the voltage on that side of the cell such that the inverters cross-couple more quickly In either case, this “write assist” feature facilitates the writing of a logic 1 value into the cell without hindering writing of a logic 0 value into the cell. Bits cells formed in accordance with the invention can be replicated in various row arrangements to share write assist circuitry amongst pairs of cells while providing separate read/write mechanisms for each cell in a pair of cells.


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A. Silburt et al., “A 180-MHz 0.8-&mgr;m BiCMOS Modular Memory Family of DRAM and Multiport SRAM”, IEEE J. Solid State Circuits, V. 28, No. 3, Mar. 1993, pp 222-232.

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